公开(公告)号：US06417715B2

公开(公告)日：2002-07-09

申请号：US09793999

申请日：2001-02-28

申请人： Takeshi Hamamoto ,  Kiyohiro Furutani

发明人： Takeshi Hamamoto ,  Kiyohiro Furutani

IPC分类号： G06F104

CPC分类号： H03L7/0805 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03K5/135 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/089 ,  H03L7/091

摘要： A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.

摘要翻译： 时钟生成电路包括：时钟输入电路，接收互补的外部时钟以产生内部时钟;可变延迟电路，延迟内部时钟以产生内部操作时钟;复制电路进一步将内部操作时钟延迟预定时间，以产生 返回时钟，直接比较外部时钟的电位电平与返回时钟的相位相交的相位比较器的相位比较器，以及根据相位比较器的相位比较结果来调整可变延迟电路的延迟量的延迟控制电路。

公开(公告)号：US5987619A

公开(公告)日：1999-11-16

申请号：US947372

申请日：1997-10-08

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C11/409 ,  G06F1/04

CPC分类号： G06F1/10

摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.

摘要翻译： 具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下， 从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。 在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。

公开(公告)号：US5838335A

公开(公告)日：1998-11-17

申请号：US844633

申请日：1997-04-21

申请人： Takeshi Hamamoto

发明人： Takeshi Hamamoto

IPC分类号： H01L21/822 ,  G06F17/50 ,  G06T1/60 ,  H01L21/82 ,  H01L27/04

CPC分类号： G06T1/60

摘要： A graphic data processing device is proposed that enables high-speed graphic processing for repeated graphic in semiconductor layout data. A plurality of sets of systematic array graphic data are inputted in an input device, the inputted systematic array graphic data are checked in an array information analyzer to confirm that the grid widths of the array grids of the different data are equal, and data are converted at an array graphic converter to systematic array graphic data sharing common array grid information. The data can then undergo graphic processing at a graphic processor in the form of systematic array graphic data without further alteration.

摘要翻译： 提出了一种能够对半导体布局数据中的重复图形进行高速图形处理的图形数据处理装置。 在输入装置中输入多组系统阵列图形数据，在阵列信息分析器中检查输入的系统阵列图形数据，以确认不同数据的阵列网格的网格宽度相等，数据被转换 在阵列图形转换器到系统阵列图形数据共享公共阵列网格信息。 然后，数据可以以图形处理器的形式以系统阵列图形数据的形式进行图形处理，而无需进一步的改变。

公开(公告)号：US5736760A

公开(公告)日：1998-04-07

申请号：US632321

申请日：1996-04-15

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5548145A

公开(公告)日：1996-08-20

申请号：US328526

申请日：1994-10-25

申请人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

发明人： Takeshi Hamamoto ,  Takashi Yamada ,  Yutaka Ishibashi

IPC分类号： H01L27/108

CPC分类号： H01L27/108 ,  H01L27/10829

摘要： A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode. Each of the capacitors includes a charge storage layer formed on an inner wall of each of the trenches and connected integrally to one of the source and drain regions of each of the transistors, a capacitor insulating film formed on the charge storage layer and a capacitor electrode formed on the capacitor insulating film so as to bury each of the trenches and extending to the surface of the substrate, which is formed on the surface of the substrate except for at least formation areas of the transistors.

摘要翻译： 一种半导体存储器件包括具有存储单元区域的半导体衬底，选择性地形成在存储单元区域中以一定间隔对准的多个沟槽和设置在存储单元区域中的多个存储单元阵列，其中每个存储单元阵列包括 以串联阵列连接的多个MOS晶体管和分别形成在对应的一个沟槽中的多个电容器。 每个晶体管在衬底之上具有栅极电极，栅极绝缘膜形成在其间，源极和漏极区域形成在栅电极两侧的衬底中。 每个电容器包括形成在每个沟槽的内壁上并且与每个晶体管的源极和漏极区中的一个一体连接的电荷存储层，形成在电荷存储层上的电容器绝缘膜和电容器电极 形成在电容器绝缘膜上，以埋入每个沟槽并且延伸到形成在基板的表面上的基板的表面，除了晶体管的至少形成区域之外。

公开(公告)号：US5418923A

公开(公告)日：1995-05-23

申请号：US937763

申请日：1992-09-01

申请人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

发明人： Masaaki Mihara ,  Tadato Yamagata ,  Takeshi Hamamoto

IPC分类号： G11C15/04 ,  G11C15/00

CPC分类号： G11C15/04

摘要： An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.

摘要翻译： 当从联想存储器获得符合信号时，编码电路将一致信号所需的时间缩短为根据预定的优先级依次选择和输出之后被转换成地址码。 该电路设置有用于较低子组的竞争仲裁电路和用于较高子组的争用仲裁电路。 在用于较低子组的竞争仲裁电路和较高子组的竞争仲裁电路中，每个符合信号同时激活优先级低于一致信号的优先级的禁止信号。 在下一个子组的竞争仲裁电路中，按照降序排列下半部分的符合信号，并且在较高子组的竞争仲裁电路中按照升序排列较高的一半符号信号。 用于较低子组的争用仲裁电路和用于较高子组的争用仲裁电路分别以三角阵列和互补三角阵列排列。

公开(公告)号：US5388066A

公开(公告)日：1995-02-07

申请号：US084098

申请日：1993-07-01

申请人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

发明人： Takeshi Hamamoto ,  Tadato Yamagata ,  Masaaki Mihara

IPC分类号： G06F17/30 ,  G11C15/00 ,  G11C15/04

CPC分类号： G06F17/30982 ,  G11C15/00 ,  G11C15/04 ,  G11C15/043

摘要： A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.

摘要翻译： 一种数据存储电路，其特征在于，具备排列成多个行和列的存储单元以及对应于各行的标志单元，用于存储标志信息，存储单元和构成一个字的同一行的标志单元。 当外部应用检索数据时，将包括在检索数据中的数据与存储单元的数据进行比较，并将存储在检索数据中的标志信息与存储在标志单元中的标志进行比较。 比较结果输出到匹配行。 逻辑运算电路根据比较结果输出到匹配线进行逻辑运算，并将逻辑输出写入数据存储电路的标志单元。

公开(公告)号：US5319589A

公开(公告)日：1994-06-07

申请号：US966921

申请日：1992-10-27

申请人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

发明人： Tadato Yamagata ,  Masaaki Mihara ,  Takeshi Hamamoto ,  Hideyuki Ozaki

IPC分类号： G11C15/00 ,  G11C11/4094 ,  G11C15/04 ,  G11C29/04

CPC分类号： G11C11/4094 ,  G11C15/043

摘要： A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

摘要翻译： 公开了一种用于实现动态内容可寻址存储器的位线控制电路。 位线控制电路包括读取电路12和连接到数据线对DT，/ DT的第一写入电路13，读出放大器14，位线放电电路15，位线充电电路16，传输门电路17 和第二写入电路18.位线控制电路通过位线BLa，/ BLa连接到CAM单元阵列。 可以通过简单的电路配置在简单的定时控制下，在动态关联存储器中所需的诸如写入，读取，刷新和匹配检测等各种操作。

公开(公告)号：US4965767A

公开(公告)日：1990-10-23

申请号：US380428

申请日：1989-07-17

申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

IPC分类号： G11C15/04

CPC分类号： G11C15/043 ,  G11C15/04

摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。