公开(公告)号：US06808987B2

公开(公告)日：2004-10-26

申请号：US10460796

申请日：2003-06-12

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for forming a vertical nitride read-only memory cell. A substrate having at least one trench is provided. A first conductive layer is formed in the lower trench and insulated from the substrate to serve as a source line. A first doping region is formed in the substrate adjacent to the top of the first conductive layer. A first insulating layer is formed on the first conductive layer. A second doping region is formed in the substrate adjacent to the top of the trench. A second insulating layer is formed over the sidewall of the trench and on the first insulating layer to serve as a gate dielectric layer. A second conductive layer is formed in the upper trench to serve as a control gate. A vertical nitride read-only memory cell is also disclosed.

Abstract translation: 一种用于形成垂直氮化物只读存储单元的方法。 提供具有至少一个沟槽的衬底。 第一导电层形成在下沟槽中并与衬底绝缘以用作源极线。 第一掺杂区形成在与第一导电层的顶部相邻的衬底中。 在第一导电层上形成第一绝缘层。 第二掺杂区形成在邻近沟槽顶部的衬底中。 第二绝缘层形成在沟槽的侧壁和第一绝缘层上，用作栅极介电层。 第二导电层形成在上沟槽中用作控制栅极。 还公开了一种垂直氮化物只读存储单元。

公开(公告)号：US20140252532A1

公开(公告)日：2014-09-11

申请号：US13792231

申请日：2013-03-11

Applicant: Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

Inventor： Sheng-Wei Yang ,  Ying-Cheng Chuang ,  Shyam Surthi

IPC: H01L29/06 ,  H01L21/765

CPC classification number: H01L21/765 ,  H01L21/265 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/10876 ,  H01L29/0607 ,  H01L29/407 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827

Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.

Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤。 提供具有多个支柱的基板，其中围绕每个支柱形成多个沟槽。 在衬底中并在每个柱下方形成掺杂区域。 去除每个沟槽下方的掺杂区域以形成开口，使得相邻支柱之下的掺杂区域彼此分离。 在每个开口中形成屏蔽层。

公开(公告)号：US06670246B1

公开(公告)日：2003-12-30

申请号：US10465178

申请日：2003-06-19

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC: H01L21336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for forming a vertical nitride read-only memory cell. First, a substrate having at least one trench is provided. Next, a masking layer is formed over the sidewall of the trench. Next, ion implantation is performed on the substrate to respectively form doping areas in the substrate near its surface and the bottom of the substrate trench to serve as bit lines. Next, bit line oxides are formed over each of the doping areas and an oxide layer is formed overlying the mask layer by thermal oxidation. Finally, a conductive layer is formed overlying the bit line oxides and fills in the trench to serve as a word line.

Abstract translation: 一种用于形成垂直氮化物只读存储单元的方法。 首先，提供具有至少一个沟槽的衬底。 接下来，在沟槽的侧壁上形成掩模层。 接下来，在衬底上进行离子注入，以分别在衬底的表面和底部附近在衬底中形成掺杂区域，以用作位线。 接下来，在每个掺杂区域上形成位线氧化物，并且通过热氧化在掩模层上形成氧化物层。 最后，形成覆盖位线氧化物的导电层并填充在沟槽中以用作字线。

公开(公告)号：US08334196B2

公开(公告)日：2012-12-18

申请号：US12917339

申请日：2010-11-01

Applicant: Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

Inventor： Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L27/10876 ,  H01L21/28531 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract translation: 形成导电接触的方法包括形成包括与侧壁表面接合的上表面的结构。 侧壁表面含有元素型硅。 硅从侧壁表面外延生长。 电介质材料形成在上表面和外延生长的硅上。 通过电介质材料形成导电接触，以与上表面导电连接。

公开(公告)号：US20060088967A1

公开(公告)日：2006-04-27

申请号：US11114735

申请日：2005-04-26

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

Abstract: The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the substrate to form one or more semiconductor fins standing between the trenches as an active region, such as a source, drain, and channel for the FinFET transistor.

Abstract translation: 本发明提供一种制造FinFET晶体管的方法，包括以下步骤：在半导体衬底中形成多个沟槽，在半导体衬底上形成电介质层并填充沟槽，并将电介质层回蚀刻到低于 衬底的表面以形成一个或多个位于沟槽之间的半导体鳍片作为有源区域，例如用于FinFET晶体管的源极，漏极和沟道。

公开(公告)号：US20050087823A1

公开(公告)日：2005-04-28

申请号：US10994018

申请日：2004-11-19

Applicant: Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract translation: 只读存储单元（ROM）及其制造方法。 电池包括衬底，多个位线，多个位线氧化物，栅极电介质层和字线。 在基板的表面附近形成位线。 位线氧化物位于位线之上。 栅介电层设置在位线之间的衬底上，并且还包括富硅氧化物层。 字线设置在位线氧化物和栅极电介质层之上。