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36 条记录 (耗时 0.028 秒)

    Floating gate and fabricating method thereof
    5.
    发明申请
    Floating gate and fabricating method thereof 有权
    浮栅及其制造方法

    公开(公告)号：US20070063260A1

    公开(公告)日：2007-03-22

    申请号：US11603771

    申请日：2006-11-22

    申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

    摘要： A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

    摘要翻译： 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

    Stack gate with tip vertical memory and method for fabricating the same
    6.
    发明授权
    Stack gate with tip vertical memory and method for fabricating the same 有权
    具有尖端垂直存储器的堆叠门及其制造方法

    公开(公告)号：US07022573B2

    公开(公告)日：2006-04-04

    申请号：US10884701

    申请日：2004-07-02

    申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

    发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

    摘要： A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

    摘要翻译： 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。

    Floating gate and fabrication method therefor
    7.
    发明申请
    Floating gate and fabrication method therefor 审中-公开
    浮门及其制造方法

    公开(公告)号：US20050101090A1

    公开(公告)日：2005-05-12

    申请号：US11014483

    申请日：2004-12-15

    申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/336

    CPC分类号： H01L29/42324 ,  H01L29/40114

    摘要： A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

    摘要翻译： 具有多个尖端的浮动栅极及其制造方法。 提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。 在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。 间隔件形成在开口的侧壁上。 导电间隔件形成在间隔件的侧壁上。 第一导电层被蚀刻到第二预定厚度。 由第一导电层和导电间隔物提供多尖端浮栅。 在开口中形成保护层。 蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。

    Memory structure and fabricating method thereof
    8.
    发明申请
    Memory structure and fabricating method thereof 审中-公开
    存储器结构及其制造方法

    公开(公告)号：US20080283895A1

    公开(公告)日：2008-11-20

    申请号：US11953882

    申请日：2007-12-11

    申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

    发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang

    IPC分类号： H01L29/00 ,  H01L21/425

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively.

    摘要翻译： 描述了包括衬底，电介质图案，间隔物图案，第一介电层，导体图案，第二电介质层和掺杂区域的存储器结构。 电介质图案设置在基板上。 间隔图案分别设置在每个电介质图案的每个侧壁上。 第一介电层设置在间隔物图案和基板之间。 导体图案设置在基板上并覆盖间隔图案。 第二电介质层设置在间隔物图案和导体图案之间。 掺杂区域分别设置在每个电介质图案下的衬底中。

    Method for fabricating floating gate
    9.
    发明授权
    Method for fabricating floating gate 有权
    浮栅制造方法

    公开(公告)号：US06921694B2

    公开(公告)日：2005-07-26

    申请号：US10442308

    申请日：2003-05-19

    申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/336

    CPC分类号： H01L29/42324 ,  H01L21/28273

    摘要： A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

    摘要翻译： 一种用于制造具有多个尖端的浮动栅极的方法。 提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。 图案化的硬掩模层具有露出半导体衬底的表面的开口。 在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。 导电层被平坦化以暴露图案化的硬掩模层的表面。 导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。

    VERTICAL DRAM AND FABRICATION METHOD THEREOF
    10.
    发明申请
    VERTICAL DRAM AND FABRICATION METHOD THEREOF 有权
    垂直DRAM及其制造方法

    公开(公告)号：US20050127422A1

    公开(公告)日：2005-06-16

    申请号：US10707396

    申请日：2003-12-10

    申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

    发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

    摘要： A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

    摘要翻译： 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。