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149 条记录 (耗时 0.034 秒)

    Semiconductor memory
    31.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US08705270B2

    公开(公告)日：2014-04-22

    申请号：US13415662

    申请日：2012-03-08

    申请人： Masahiro Takahashi ,  Yoshihiro Ueda

    发明人： Masahiro Takahashi ,  Yoshihiro Ueda

    IPC分类号： G11C11/00 ,  G11C11/16

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

    摘要： A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.

    摘要翻译： 半导体存储器具有第一开关电路和第二开关电路。 半导体存储器具有控制字线电压的行解码器。 半导体存储器具有第一写入电路，该第一写入电路包括连接到第一开关电路的一端的第一信号端子，以输入和输出写入电流。 半导体存储器具有第二写入电路，该第二写入电路包括连接到第二开关电路的一端的第二信号端子，以输入和输出写入电流。 半导体存储器具有包括连接到字线的控制端的选择晶体管。 半导体存储器具有与第一位线和第二位线之间的选择晶体管串联连接的电阻变化元件，并根据所施加的电流而变化电阻值。

    Semiconductor memory
    32.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US08630136B2

    公开(公告)日：2014-01-14

    申请号：US13422110

    申请日：2012-03-16

    申请人： Yoshihiro Ueda ,  Kosuke Hatsuda

    发明人： Yoshihiro Ueda ,  Kosuke Hatsuda

    IPC分类号： G11C7/00

    CPC分类号： G11C11/1673

    摘要： A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell.

    摘要翻译： 半导体存储器包括：第一存储单元，包括：第一电阻变化元件和第一选择晶体管。 半导体存储器包括第二存储单元，其包括：第二选择晶体管和第二电阻变化元件。 半导体存储器包括第三存储单元，第三存储单元包括：第三选择晶体管和第三电阻变化元件，第三存储单元用作参考单元。 半导体存储器包括：第四存储单元，包括：第四电阻变化元件和第四选择晶体管，第四存储单元用作参考单元。

    Semiconductor storage device
    33.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US08498144B2

    公开(公告)日：2013-07-30

    申请号：US13191678

    申请日：2011-07-27

    申请人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

    发明人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

    IPC分类号： G11C11/00 ,  G11C11/15

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

    摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

    摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

    RESISTANCE CHANGE TYPE MEMORY
    34.
    发明申请
    RESISTANCE CHANGE TYPE MEMORY 审中-公开
    电阻变化型存储器

    公开(公告)号：US20120243297A1

    公开(公告)日：2012-09-27

    申请号：US13428312

    申请日：2012-03-23

    申请人： Akira KATAYAMA ,  Yoshihiro Ueda

    发明人： Akira KATAYAMA ,  Yoshihiro Ueda

    IPC分类号： G11C11/00

    CPC分类号： G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0073

    摘要： According to one embodiment, a resistance change type memory includes first to third bit lines, a word line and a memory cell connected to the first to third bit lines and the word line. The memory cell includes a first transistor and a first memory element between the first and third bit lines, a second transistor and a second memory element between the second and third bit lines. Control terminals of the first and second transistors are connected to the word line. The resistance states of the first and second memory elements change to the first or second resistance state in accordance with a write pulse.

    摘要翻译： 根据一个实施例，电阻变化型存储器包括第一至第三位线，字线和连接到第一至第三位线和字线的存储单元。 存储单元包括第一和第三位线之间的第一晶体管和第一存储元件，第二晶体管和第二位线之间的第二存储元件。 第一和第二晶体管的控制端连接到字线。 根据写入脉冲，第一和第二存储元件的电阻状态变为第一或第二电阻状态。

    SEMICONDUCTOR STORAGE DEVICE
    35.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 失效
    半导体存储设备

    公开(公告)号：US20120063215A1

    公开(公告)日：2012-03-15

    申请号：US13191678

    申请日：2011-07-27

    申请人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

    发明人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

    摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

    摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

    Secure document management using distributed hashing
    36.
    发明授权
    Secure document management using distributed hashing 有权
    使用分布式散列的安全文档管理

    公开(公告)号：US08086570B2

    公开(公告)日：2011-12-27

    申请号：US11282022

    申请日：2005-11-17

    申请人： Shigehisa Kawabe ,  Setsu Kunitake ,  Yoshihiro Ueda ,  Kenichi Numata ,  Akira Suzuki ,  Masao Nukaga ,  Taro Terao ,  Meng Shi

    发明人： Shigehisa Kawabe ,  Setsu Kunitake ,  Yoshihiro Ueda ,  Kenichi Numata ,  Akira Suzuki ,  Masao Nukaga ,  Taro Terao ,  Meng Shi

    IPC分类号： G06F7/00 ,  G06F17/00

    CPC分类号： G06F17/30011

    摘要： The document management server includes an identification information providing unit that receives a request to obtain identification information required for accessing a document from a client, generates the identification information for the received request, and sends the generated identification information to the client; a relation information management unit that manages relation information of the requested document and the identification information generated for the request; and a history information management unit that manages information on the client who has sent the request, associating with the identification information.

    摘要翻译： 文件管理服务器包括识别信息提供单元，其接收从客户端获取文档所需的识别信息的请求，生成接收到的请求的识别信息，并将生成的识别信息发送给客户端; 关系信息管理单元，其管理所请求的文档的关系信息和为该请求生成的识别信息; 以及历史信息管理单元，其管理已经发送请求的客户端的信息，与该识别信息相关联。

    Semiconductor memory device
    37.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08040718B2

    公开(公告)日：2011-10-18

    申请号：US12559311

    申请日：2009-09-14

    申请人： Yoshihiro Ueda

    发明人： Yoshihiro Ueda

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

    摘要： A semiconductor memory device includes a memory cell having a first resistance state and a second resistance state, a bit line connected to the memory cell, a reference cell fixed to the first resistance state, a reference bit line connected to the reference cell, and a generation circuit configured to generate a reading voltage and a reference voltage. The generation circuit includes a constant current source connected to a first node, a first replica cell connected between the first node and a second node and fixed to the first resistance state, a second replica cell connected between the second node and a third node and fixed to the second resistance state, a first resistance element connected between the first node and a fourth node, and a second resistance element connected between the fourth node and the third node.

    摘要翻译： 半导体存储器件包括具有第一电阻状态和第二电阻状态的存储单元，连接到存储单元的位线，固定到第一电阻状态的参考单元，连接到参考单元的参考位线，以及 所述发生电路被配置为产生读取电压和参考电压。 所述生成电路包括连接到第一节点的恒流源，连接在所述第一节点和第二节点之间并固定到所述第一电阻状态的第一副本单元，连接在所述第二节点和第三节点之间并固定的第二复制单元 连接到第二电阻状态，连接在第一节点和第四节点之间的第一电阻元件以及连接在第四节点和第三节点之间的第二电阻元件。

    INTERFACE CARD SYSTEM
    38.
    发明申请
    INTERFACE CARD SYSTEM 有权
    界面卡系统

    公开(公告)号：US20110238880A1

    公开(公告)日：2011-09-29

    申请号：US12771072

    申请日：2010-04-30

    申请人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

    发明人： Katsuhiro Hirayama ,  Hiroto Yoshikawa ,  Yoshihiro Ueda ,  Osamu Mikami

    IPC分类号： G06F13/00 ,  G06F13/28

    CPC分类号： G06F13/385 ,  G06F2213/3804

    摘要： There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

    摘要翻译： 提供了一种用于SD总线控制的接口卡系统。 用于SD总线控制的接口卡系统包括CPU总线接口11a和/或SD总线接口11b，连接到解释SD命令并控制整个接口卡系统的操作的接口的主机接口模块16 和用作主机控制器的第二内部SD主机引擎15a和15b，分别连接到内部SD主机引擎的第一和第二选择器14a和14b，每个内部SD主机引擎选择数据或命令的路径，第一和第二SD总线接口13a和 13b，以及连接到连接到选择器的SD总线接口的数据传递控制部分17，其允许SD命令和数据通过。