公开(公告)号：US08498144B2

公开(公告)日：2013-07-30

申请号：US13191678

申请日：2011-07-27

申请人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

发明人： Masahiro Takahashi ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

IPC分类号： G11C11/00 ,  G11C11/15

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

公开(公告)号：US20120063215A1

公开(公告)日：2012-03-15

申请号：US13191678

申请日：2011-07-27

申请人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

发明人： Masahiro TAKAHASHI ,  Katsuyuki Fujita ,  Yoshihiro Ueda ,  Katsuhiko Hoya

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/1675 ,  G11C11/1693

摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.

摘要翻译： 半导体存储装置包括第一至第四开关电路。 半导体存储装置包括用于控制字线电压的行译码器。 半导体存储装置包括控制端子连接到字线的第一选择晶体管。 半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。 半导体存储装置包括控制端子连接到字线的第二选择晶体管。 半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

公开(公告)号：US08498145B2

公开(公告)日：2013-07-30

申请号：US13205094

申请日：2011-08-08

申请人： Katsuyuki Fujita ,  Yoshihiro Ueda

发明人： Katsuyuki Fujita ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/14 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1675

摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.

摘要翻译： 存储器包括连接在第一和第二BL之间的位线，字线和存储单元。 布置在BL的延伸方向上的单元构成列。 第二个BL在两列之间共享。 第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。 该装置包括与相邻存储元件具有相等距离的虚拟单元。 此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。 每个单元包含选择晶体管。 选择晶体管并联连接在存储元件和第一BL之间。 晶体管的栅极连接到不同的WL。

公开(公告)号：US20120063216A1

公开(公告)日：2012-03-15

申请号：US13205094

申请日：2011-08-08

申请人： Katsuyuki Fujita ,  Yoshihiro Ueda

发明人： Katsuyuki Fujita ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/14 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1675

摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.

摘要翻译： 存储器包括连接在第一和第二BL之间的位线，字线和存储单元。 布置在BL的延伸方向上的单元构成列。 第二个BL在两列之间共享。 第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。 该装置包括与相邻存储元件具有相等距离的虚拟单元。 此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。 每个单元包括选择晶体管。 选择晶体管并联连接在存储元件和第一BL之间。 晶体管的栅极连接到不同的WL。

公开(公告)号：US08705270B2

公开(公告)日：2014-04-22

申请号：US13415662

申请日：2012-03-08

申请人： Masahiro Takahashi ,  Yoshihiro Ueda

发明人： Masahiro Takahashi ,  Yoshihiro Ueda

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.

摘要翻译： 半导体存储器具有第一开关电路和第二开关电路。 半导体存储器具有控制字线电压的行解码器。 半导体存储器具有第一写入电路，该第一写入电路包括连接到第一开关电路的一端的第一信号端子，以输入和输出写入电流。 半导体存储器具有第二写入电路，该第二写入电路包括连接到第二开关电路的一端的第二信号端子，以输入和输出写入电流。 半导体存储器具有包括连接到字线的控制端的选择晶体管。 半导体存储器具有与第一位线和第二位线之间的选择晶体管串联连接的电阻变化元件，并根据所施加的电流而变化电阻值。

公开(公告)号：US20120230090A1

公开(公告)日：2012-09-13

申请号：US13415662

申请日：2012-03-08

申请人： Masahiro Takahashi ,  Yoshihiro Ueda

发明人： Masahiro Takahashi ,  Yoshihiro Ueda

IPC分类号： G11C11/16

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675

摘要： A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.

摘要翻译： 半导体存储器具有第一开关电路和第二开关电路。 半导体存储器具有控制字线电压的行解码器。 半导体存储器具有第一写入电路，该第一写入电路包括连接到第一开关电路的一端的第一信号端子，以输入和输出写入电流。 半导体存储器具有第二写入电路，该第二写入电路包括连接到第二开关电路的一端的第二信号端子，以输入和输出写入电流。 半导体存储器具有包括连接到字线的控制端的选择晶体管。 半导体存储器具有与第一位线和第二位线之间的选择晶体管串联连接的电阻变化元件，并且根据所施加的电流而改变电阻值。

公开(公告)号：US09415686B2

公开(公告)日：2016-08-16

申请号：US14361737

申请日：2012-12-25

申请人： Yoshihiro Ueda ,  Hitoshi Sugiyama ,  Shigeo Katoh

发明人： Yoshihiro Ueda ,  Hitoshi Sugiyama ,  Shigeo Katoh

IPC分类号： B60K37/02 ,  B60K35/00 ,  G06F3/14 ,  G01C21/36 ,  H04N21/472 ,  G06F5/00

CPC分类号： B60K37/02 ,  B60K35/00 ,  B60K2350/1096 ,  B60K2350/352 ,  G01C21/36 ,  G01C21/3602 ,  G06F3/1423 ,  G06F5/00 ,  G09G2380/10 ,  H04N21/472

摘要： A display control apparatus, with respect to multiple display areas of a display screen of a display apparatus, assigns one display image to one of the display areas by performing a predetermined calculation. The display control apparatus includes a display image managing section storing image information related to the display image, a display area managing section storing area information related to each display area, a mandatory exclusion information storing section storing mandatory exclusion information that defines multiple display image combinations so that the display image is included in each of the display image combinations, and a display image assignment control section. The display image assignment control section, based on the mandatory exclusion information, determines the display image combinations, generates a display image combination list, and assigns the display image to the display area based on the display image combination list.

摘要翻译： 显示控制装置相对于显示装置的显示画面的多个显示区域，通过执行预定的计算将一个显示图像分配给一个显示区域。 显示控制装置包括存储与显示图像相关的图像信息的显示图像管理部分，存储与每个显示区域相关的区域信息的显示区域管理部分，存储限定多个显示图像组合的强制排除信息的强制排除信息存储部分 显示图像被包括在每个显示图像组合中，以及显示图像分配控制部分。 显示图像分配控制部分基于强制排除信息确定显示图像组合，生成显示图像组合列表，并且基于显示图像组合列表将显示图像分配给显示区域。

公开(公告)号：US08858073B2

公开(公告)日：2014-10-14

申请号：US13421047

申请日：2012-03-15

申请人： Hiroyuki Tada ,  Masato Asahara ,  Yoshihiro Ueda ,  Hideki Aoki ,  Akira Minoura

发明人： Hiroyuki Tada ,  Masato Asahara ,  Yoshihiro Ueda ,  Hideki Aoki ,  Akira Minoura

IPC分类号： G01K1/08 ,  G01K13/02

摘要： An exhaust gas temperature detection sensor is arranged at a predetermined position outside a muffler, or at a predetermined position outside an exhaust pipe constituting an exhaust gas flow passage on a more downstream side than the muffler in an exhaust direction. The sensor detects that an atmosphere temperature at the predetermined position outside the muffler has reached a predetermined temperature based on an increase in a temperature inside the muffler, or detects that an atmosphere temperature at the predetermined position outside the exhaust pipe has reached a predetermined temperature based on an increase in a temperature of an exhaust gas inside the exhaust pipe.

公开(公告)号：US20140114531A1

公开(公告)日：2014-04-24

申请号：US14127713

申请日：2012-08-09

申请人： Hitoshi Sugiyama ,  Shigeo Kato ,  Yoshihiro Ueda

发明人： Hitoshi Sugiyama ,  Shigeo Kato ,  Yoshihiro Ueda

IPC分类号： B60R1/00

CPC分类号： G01C21/3602 ,  B60K35/00 ,  B60K2350/1076 ,  B60K2350/1096 ,  B60K2350/352 ,  G01C21/3632 ,  G01C21/3647 ,  G01C21/3658 ,  G06F3/0481 ,  G06F3/1423 ,  G06F5/00 ,  G09G5/14 ,  G09G2340/0464 ,  G09G2340/14 ,  H04N21/4314 ,  H04N21/472

摘要： A display control apparatus for controlling a display device including a screen having a plurality of areas so as to assign and display a content on a corresponding area, includes: a content managing unit managing the content by associating content information; an area managing unit managing the area by associating area information; and a content assignment control unit determining a combination of the content and the area. The content assignment control unit generates a content list, generates an area list, extracts a combination list based on the area list and the content list, calculates an evaluation reference value of each combination list based on the content information and the area information, selects the combination list based on the evaluation reference value of each combination list, and determines a combination.

摘要翻译： 一种显示控制装置，用于控制包括具有多个区域的屏幕的显示装置，以便在相应区域上分配和显示内容，包括：内容管理单元，通过关联内容信息来管理内容; 区域管理单元，通过关联区域信息来管理该区域; 以及内容分配控制单元，确定内容和区域的组合。 内容分配控制单元生成内容列表，生成区域列表，基于区域列表和内容列表提取组合列表，基于内容信息和区域信息来计算各组合列表的评价基准值， 基于每个组合列表的评估参考值的组合列表，并且确定组合。

公开(公告)号：US08548677B2

公开(公告)日：2013-10-01

申请号：US13397866

申请日：2012-02-16

申请人： Hitoshi Sugiyama ,  Shigeo Katoh ,  Yoshihiro Ueda

发明人： Hitoshi Sugiyama ,  Shigeo Katoh ,  Yoshihiro Ueda

IPC分类号： G06F7/00 ,  B60Q1/00 ,  G09G5/00 ,  G06F5/00

CPC分类号： G06F5/00 ,  B60Q1/00 ,  G09G5/00 ,  G09G5/14

摘要： A content management section rearranges contents in an order from a content having a greater information value, preparing a content list. With respect to assignable areas of a display apparatus, a region value is compared with an information value of each content; the content may be assigned to the area when the information value exceeds the region value. The contents are associated with information values and the areas are associated with region values; thus, the content can be assigned to the area that is more suitable. When there are several assignable areas, a target content is assigned to an area having a highest region value.

摘要翻译： 内容管理部分从具有较大信息值的内容中按顺序重新排列内容，准备内容列表。 对于显示装置的可分配区域，将区域值与每个内容的信息值进行比较; 当信息值超过区域值时，可以将内容分配给区域。 内容与信息值相关联，区域与区域值相关联; 因此，可以将内容分配给更合适的区域。 当存在多个可分配区域时，将目标内容分配给具有最高区域值的区域。