公开(公告)号：US20230396217A1

公开(公告)日：2023-12-07

申请号：US18328987

申请日：2023-06-05

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F1/22 ,  H03F1/30 ,  H03F3/189

CPC classification number: H03F1/0227 ,  H03F1/56 ,  H03F3/193 ,  H03F1/223 ,  H03F1/301 ,  H03F3/189 ,  H03F2200/18 ,  H03F2200/453 ,  H03F2200/249

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

公开(公告)号：US11711068B2

公开(公告)日：2023-07-25

申请号：US17094654

申请日：2020-11-10

Applicant: pSemi Corporation

Inventor： John Birkbeck ,  Vikas Sharma ,  Kashish Pal ,  Mark James O'Leary

IPC: H03H11/20 ,  H03H11/26 ,  H03H17/08 ,  H03H17/00

CPC classification number: H03H11/20 ,  H03H11/265 ,  H03H17/0009 ,  H03H17/0054 ,  H03H17/08

Abstract: A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

公开(公告)号：US20220158589A1

公开(公告)日：2022-05-19

申请号：US17531510

申请日：2021-11-19

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal ,  Robert Mark Englekirk ,  Tero Tapio Ranta ,  Keith Bargroff ,  Simon Edward Willard

IPC: H03F1/02 ,  H03F3/193 ,  H03F1/22

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

公开(公告)号：US20200343862A1

公开(公告)日：2020-10-29

申请号：US15931236

申请日：2020-05-13

Applicant: pSemi Corporation

Inventor： Kashish Pal ,  Emre Ayranci ,  Miles Sanner

IPC: H03F1/22 ,  H03F3/193 ,  H03F1/26 ,  H04L27/26 ,  H03F3/68

Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

公开(公告)号：US10819288B2

公开(公告)日：2020-10-27

申请号：US16283298

申请日：2019-02-22

Applicant: pSemi Corporation

Inventor： Poojan Wagh ,  Kashish Pal

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F1/22 ,  H03F1/30 ,  H03F3/189

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

公开(公告)号：US10326484B1

公开(公告)日：2019-06-18

申请号：US16001871

申请日：2018-06-06

Applicant: pSemi Corporation

Inventor： Emre Ayranci ,  Miles Sanner ,  Phanindra Yerramilli ,  Kashish Pal

IPC: H04B1/16 ,  H03F3/19

Abstract: A front end module having reduced number of low noise amplifier (LNAs) for receiving various combinations of contiguous aggregation (CA) signals and non-CA signals having different combinations of signals aggregated therein. The FECC can include a broadband LNA and/or a band-switching LNA having at least two modes of operation. An input switch directs a received signal to one of several banks of filters. LNA switches direct the signals from the output of filters within a selected filter bank to particular LNAs. LNAs may be connected by LNA switches to filters in more than one filter bank. The proper mode of operation is selected for the band switching LNA based on the particular frequencies present in the received signal and the filters selected.