公开(公告)号：US20140062444A1

公开(公告)日：2014-03-06

申请号：US14071305

申请日：2013-11-04

Applicant: Jing-Meng Liu

Inventor： Jing-Meng Liu

IPC: H02M3/156

CPC classification number: H02M3/156

Abstract: A boundary conduction mode (BCM) switching regulator controls a power stage to convert an input voltage to an output voltage or output current. The BCM switching regulator detects whether it is operating in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), and adjusts the On-time, Off-time, or frequency of the power stage accordingly, so that the switching regulator operates in or near BCM.

Abstract translation: 边界导通模式（BCM）开关稳压器控制功率级将输入电压转换为输出电压或输出电流。 BCM开关稳压器检测其是工作在连续导通模式（CCM）还是不连续导通模式（DCM），并相应调整功率级的导通时间，关断时间或频率，以使开关稳压器工作在 或BCM附近。

公开(公告)号：US08525258B2

公开(公告)日：2013-09-03

申请号：US12817413

申请日：2010-06-17

Applicant: Tsung-Yi Huang ,  Ying-Shiou Lin

Inventor： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC: H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659

Abstract: The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.

Abstract translation: 本发明公开了一种用于控制半导体器件中的杂质浓度分布的方法和由此制成的半导体器件。 控制方法包括以下步骤：提供基板; 限定包括至少一个第一区域的掺杂区域; 通过掩模图案部分地掩蔽所述第一区域; 以及在所述掺杂区域中掺杂杂质以在所述第一区域中形成一个积分掺杂区域，由此所述第一区域的杂质浓度低于所述第一区域未被所述掩模图案掩蔽的情况。

公开(公告)号：US20130181522A1

公开(公告)日：2013-07-18

申请号：US13352020

申请日：2012-01-17

Applicant: Hsuan-Kai Wang ,  Nien-Hui Kung

Inventor： Hsuan-Kai Wang ,  Nien-Hui Kung

IPC: H02J1/04 ,  H02J7/34

CPC classification number: H02J7/0022 ,  H02J2007/0062 ,  Y10T307/422

Abstract: A power management control circuit controls a first power transistor to convert a input voltage to an output voltage and controls a second power transistor to charge a battery from the output voltage. The first power transistor is coupled between the input voltage and the output voltage, and the second power transistor is coupled between the output voltage and the battery. The power management control circuit includes: a detection transistor detecting a current through the second power transistor and generating a charging reference voltage; an amplifier comparing the output voltage with the voltage of the battery to generate an amplified signal for controlling the charging reference voltage; a comparator comparing a reference voltage with the charging reference voltage to generate an EOC (End of Charge) signal for determining whether to stop charging the battery; and an offset voltage compensation device compensating an input offset voltage of the amplifier.

Abstract translation: 功率管理控制电路控制第一功率晶体管以将输入电压转换为输出电压，并且控制第二功率晶体管以从输出电压对电池充电。 第一功率晶体管耦合在输入电压和输出电压之间，第二功率晶体管耦合在输出电压和电池之间。 电源管理控制电路包括：检测晶体管，检测通过第二功率晶体管的电流并产生充电参考电压; 放大器，其将输出电压与电池的电压进行比较，以产生用于控制充电参考电压的放大信号; 将参考电压与充电参考电压进行比较以产生用于确定是否停止对电池充电的EOC（充电结束）信号的比较器; 以及补偿放大器的输入偏移电压的偏移电压补偿装置。

公开(公告)号：US20130119957A1

公开(公告)日：2013-05-16

申请号：US13294203

申请日：2011-11-11

Applicant: Nien-Hui Kung

Inventor： Nien-Hui Kung

IPC: G05F5/00

CPC classification number: H02M3/1582 ,  H02M2001/0045

Abstract: The present invention discloses a bi-directional switching regulator and its control circuit, wherein the bi-directional switching regulator converts an input voltage to an output voltage in a power supply mode, and it includes: a power stage including an upper gate switch, a lower gate switch and an inductor coupled to a common switching node, wherein the inductor is coupled to the input voltage; a load switch coupled between the output voltage and the upper gate switch; and a driver circuit controlling the load switch to adjust an output current flowing through the load switch according to current information at an input terminal of the input voltage.

Abstract translation: 本发明公开了一种双向开关调节器及其控制电路，其中双向开关稳压器将输入电压转换为电源模式中的输出电压，其包括：功率级，包括上栅极开关， 下栅极开关和耦合到公共开关节点的电感器，其中所述电感器耦合到所述输入电压; 耦合在输出电压和上栅极开关之间的负载开关; 以及控制所述负载开关的驱动电路，根据所述输入电压的输入端子上的电流信息调整流过所述负载开关的输出电流。

公开(公告)号：US08421150B2

公开(公告)日：2013-04-16

申请号：US13197370

申请日：2011-08-03

Applicant: Tsung-Yi Huang ,  Huan-Ping Chu

Inventor： Tsung-Yi Huang ,  Huan-Ping Chu

IPC: H01L29/76 ,  H01L31/062

CPC classification number: H01L29/0878 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.

Abstract translation: 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中，其中衬底具有上表面。 高压器件包括：形成在衬底中的第二导电型掩埋层; 第一导电型阱，其形成在上表面和埋层之间; 以及第二导电型阱，其连接到第一导电类型阱并且位于不同的水平位置。 第二导电类型阱包括井下表面，其具有第一部分和第二部分，其中第一部分直接在掩埋层的上方并电耦合到掩埋层; 并且第二部分不位于掩埋层的上方并与衬底形成PN结。

公开(公告)号：US20120326613A1

公开(公告)日：2012-12-27

申请号：US13226091

申请日：2011-09-06

Applicant: Jing-Meng Liu

Inventor： Jing-Meng Liu

IPC: H05B37/00

CPC classification number: H05B33/0815 ,  G09G3/342 ,  G09G2330/021 ,  H05B33/0827 ,  Y02B20/347

Abstract: The present invention discloses a current splitter circuit for splitting a supply current to multiple light emitting device strings of a light emitting device array. The current splitter circuit includes: a minimum selector circuit coupled to the multiple light emitting device strings to generate a minimum signal which indicates a minimum voltage of the light emitting device strings; and multiple current source circuits each including a first current source end coupled to a corresponding light emitting device string, a second current source end coupled to ground, and a current source control end receiving a current control signal related to the minimum signal, so as to control currents through the corresponding light emitting device string.

Abstract translation: 本发明公开了一种用于将电源电流分离到发光器件阵列的多个发光器件串的电流分离器电路。 当前的分路器电路包括：耦合到多个发光器件串的最小选择器电路，以产生指示发光器件串的最小电压的最小信号; 以及多个电流源电路，每个电流源电路包括耦合到对应的发光器件串的第一电流源端，耦合到地的第二电流源端和接收与最小信号相关的电流控制信号的电流源控制端，以便 控制电流通过相应的发光器件串。

公开(公告)号：US20120293082A1

公开(公告)日：2012-11-22

申请号：US13136383

申请日：2011-07-29

Applicant: Pei-Cheng Huang ,  Kuo-Chi Liu ,  Ming-Hsueh Lee ,  Shih-Hua Chien ,  Chao-Hua Wu

Inventor： Pei-Cheng Huang ,  Kuo-Chi Liu ,  Ming-Hsueh Lee ,  Shih-Hua Chien ,  Chao-Hua Wu

IPC: H05B37/00

CPC classification number: H05B33/089

Abstract: The present invention discloses a light emitting device open/short detection circuit, which is used for detecting at least one light emitting device string open/short. Each light emitting device string has a first end and a second end, wherein the first end is coupled to a voltage supply circuit to supply electrical power to the light emitting devices. The open/short detection circuit includes: an abnormal voltage detection circuit coupled to the light emitting device strings for receiving voltages of the second ends respectively and generating an abnormal voltage detection signal; a voltage setting circuit coupled to the abnormal voltage detection circuit for setting an abnormal reference level; and a determination circuit coupled to the voltage setting circuit. When the abnormal voltage detection signal is equal to or over the abnormal reference level, the determination circuit generates an open/short detection signal for an abnormal condition detected.

Abstract translation: 本发明公开了一种用于检测至少一个发光装置串开/短的发光装置开/短检测电路。 每个发光器件串具有第一端和第二端，其中第一端耦合到电压供应电路以向发光器件供电。 开/短检测电路包括：异常电压检测电路，耦合到发光器件串，用于分别接收第二端的电压并产生异常电压检测信号; 电压设定电路，与所述异常电压检测电路耦合，用于设定异常参考电平; 以及耦合到电压设置电路的确定电路。 当异常电压检测信号等于或超过异常参考电平时，确定电路产生检测到的异常状态的开/短检测信号。

公开(公告)号：US20120280320A1

公开(公告)日：2012-11-08

申请号：US13317401

申请日：2011-10-17

Applicant: Tsung-Yi Huang ,  Chien-Hao Huang

Inventor： Tsung-Yi Huang ,  Chien-Hao Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0878 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions.

Abstract translation: 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中，其中衬底包括限定器件区域的隔离区域。 高电压装置包括：位于器件区域中的掺杂有第二导电类型杂质的漂移区; 在器件区域和衬底的表面上的栅极; 以及在栅极的不同侧的器件区域中的第二导电类型源极和漏极。 从俯视图，漂移区域的第二导电型杂质的浓度沿水平方向和垂直方向大致周期性地分布。

公开(公告)号：US20120273931A1

公开(公告)日：2012-11-01

申请号：US13200161

申请日：2011-09-20

Applicant: Hsi-Chen Yang ,  Ya-Tzu Wu

Inventor： Hsi-Chen Yang ,  Ya-Tzu Wu

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/49531 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention discloses an integrated circuit (IC) chip package and a manufacturing method thereof. The IC chip package includes: a lead frame, including a lead frame array having plural conductive cells, wherein some of the conductive cells are respectively electrically connected with corresponding first extended wires; at least one redistribution layer, wherein each redistribution layer includes plural second extended wires, which are respectively electrically connected to the first extended wires or the second extended wires of another redistribution layer; and a solder array, including plural solder balls, which are electrically connected to the lead frame array.

Abstract translation: 本发明公开了一种集成电路（IC）芯片封装及其制造方法。 IC芯片封装包括：引线框架，包括具有多个导电单元的引线框阵列，其中一些导电单元分别与对应的第一延伸线电连接; 至少一个再分配层，其中每个再分布层包括多个第二延伸线，其分别电连接到另一再分布层的第一延伸线或第二延伸线; 以及包括多个焊球的焊料阵列，其电连接到引线框架阵列。

公开(公告)号：US20120267767A1

公开(公告)日：2012-10-25

申请号：US13090449

申请日：2011-04-20

Applicant: TSUNG-YI HUANG ,  Chien-Hao Huang ,  Ying-Shiou Lin

Inventor： TSUNG-YI HUANG ,  Chien-Hao Huang ,  Ying-Shiou Lin

IPC: H01L29/02 ,  H01L21/265

CPC classification number: H01L29/06 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/36

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract translation: 本发明公开了半导体重叠PN结构及其制造方法。 该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。