公开(公告)号：US08504751B2

公开(公告)日：2013-08-06

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US08462236B2

公开(公告)日：2013-06-11

申请号：US11622507

申请日：2007-01-12

Applicant: Justin Richardson

Inventor： Justin Richardson

IPC: H04N9/64 ,  H04N5/76

CPC classification number: H04N5/367 ,  H04N5/374

Abstract: An image sensor may include a shared memory resource, which can be selectively used by a digital filter for image scaling or by a defect correction circuit.

Abstract translation: 图像传感器可以包括共享存储器资源，其可以被用于图像缩放的数字滤波器或缺陷校正电路选择性地使用。

公开(公告)号：US20130097401A1

公开(公告)日：2013-04-18

申请号：US13650503

申请日：2012-10-12

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Davide Sarta

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F12/06 ,  G06F12/0607

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract translation: 一种包括多个输出的存储器管理装置，每个输出被配置为与多个存储器中的相应的一个存储器接口; 以及控制器，其被配置为使得分配给所述存储器的每个缓冲器在所述多个存储器中的每一个之间基本上相等地被划分。

公开(公告)号：US20130031313A1

公开(公告)日：2013-01-31

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。

公开(公告)号：US20110134705A1

公开(公告)日：2011-06-09

申请号：US12958622

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: G11C7/00

CPC classification number: G11C7/10 ,  G06F13/16 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04N21/426 ,  Y02D10/14

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 提供多路复用器以将控制信号和存储器事务多路复用到接口上，使得所述接口的多个连接由控制信号和存储器事务共享。

公开(公告)号：US07774397B2

公开(公告)日：2010-08-10

申请号：US11003924

申请日：2004-12-03

Applicant: Kaushik Saha ,  Srijib Narayan Maiti ,  Marco Cornero

Inventor： Kaushik Saha ,  Srijib Narayan Maiti ,  Marco Cornero

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An FFT/IFFT processor having computation logic capable of processing butterfly operations, and storage for storing the operands of butterfly operations, including a mechanism for storing the operands of multiple consecutive butterfly operations in contiguous storage locations and wherein the computation logic is capable of simultaneously accessing and processing said multiple butterfly operations.

Abstract translation: 具有能够处理蝶形运算的计算逻辑的FFT / IFFT处理器和用于存储蝶形运算操作数的存储器，包括用于在连续的存储位置存储多个连续的蝶形运算的操作数的机构，并且其中计算逻辑能够同时存取 并处理所述多个蝴蝶操作。

公开(公告)号：US20100180129A1

公开(公告)日：2010-07-15

申请号：US12642682

申请日：2009-12-18

Applicant: David Smith

Inventor： David Smith

IPC: G06F15/76 ,  G06F21/22 ,  G06F9/02 ,  G06F9/302 ,  G06F9/305 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/3853 ,  G06F9/3875

Abstract: An arrangement of arithmetic logic units carries out an operation on at least one operand, wherein the operation is determined by operation codes received by the arithmetic logic units. The operation codes and at least one operand are received on a first clock cycle. The result of the operation is output from at least one arithmetic logic unit to at least one further arithmetic logic unit. A result of the plurality of arithmetic logic units is then output on a next clock cycle.

Abstract translation: 算术逻辑单元的布置对至少一个操作数进行操作，其中由操作代码由算术逻辑单元接收的操作码确定操作。 在第一时钟周期接收操作码和至少一个操作数。 操作的结果从至少一个算术逻辑单元输出到至少一个另外的算术逻辑单元。 然后在下一个时钟周期输出多个算术逻辑单元的结果。

公开(公告)号：US07562182B2

公开(公告)日：2009-07-14

申请号：US11592735

申请日：2006-11-03

Applicant: Peter Bennett ,  Andrew Dello ,  Jonathan Smailes

Inventor： Peter Bennett ,  Andrew Dello ,  Jonathan Smailes

IPC: G06F12/00

CPC classification number: G06F13/1631 ,  G11C16/08

Abstract: A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address.

Abstract translation: 一种存储器访问系统，包括其中以页面组织数据的存储器，每个页面保存数据元素序列; 用于接收包括请求的页面地址和所请求的数据元素地址的所请求的地址的装置; 使用当前页面地址从存储器访问当前页面的逻辑; 用于以它们被保存在存储器中的顺序读出当前页面的数据元素的逻辑; 用于将请求的页面地址与当前页面地址进行比较并用于当它们不相同时发出具有所请求的页面地址的存储器访问请求的逻辑; 以及当所请求的页面地址与当前页面地址相同时可操作的逻辑，用于将所请求的数据元素地址与正被读出的数据元素的当前地址进行比较，并且当所请求的数据元素地址与当前数据元素匹配时返回数据元素 地址。

公开(公告)号：US07326968B2

公开(公告)日：2008-02-05

申请号：US11726376

申请日：2007-03-19

Applicant: Rémi Brechignac ,  Jean-Luc Diot ,  Kevin Channon ,  Eric Chistison

Inventor： Rémi Brechignac ,  Jean-Luc Diot ,  Kevin Channon ,  Eric Chistison

IPC: H01L33/00 ,  H01L31/0203

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor packaging unit mounts onto a board by solder joints. The unit includes, disposed along one axis, a semiconductor component having on a rear face protruding electrical connection lugs designed to be soldered onto the board and an external cage surrounding the component and having a rear edge designed to be soldered onto the board and a front part through which a front part of the component passes. The component and the cage are designed to axially slide with respect to one another in such a manner as to be brought into their soldering position with respect to the board and having complementary holding parts coming into contact and designed to hold them with respect to one another when they are axially removed from the soldering position and to free them with respect to one another when they are at the soldering position.

Abstract translation: 半导体封装单元通过焊点安装在板上。 该单元包括沿着一个轴布置的半导体部件，该半导体部件在后表面上突出设计成被焊接到板上的电连接凸耳和围绕该部件的外部保持架，并且具有设计成焊接到板上的后边缘和前部 组件的前部通过的部分。 组件和保持架设计成相对于彼此轴向滑动，以便相对于板进入它们的焊接位置，并且具有互补的保持部件接触并设计成相对于彼此保持它们 当它们从焊接位置轴向移除时，并且当它们处于焊接位置时相对于彼此释放。

公开(公告)号：US20140009168A1

公开(公告)日：2014-01-09

申请号：US13934786

申请日：2013-07-03

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Mark TRIMMER

IPC: G01R31/28

CPC classification number: G01R31/2832 ,  G01R31/31725

Abstract: An apparatus may include a delay line having a first delay value corresponding to first operating conditions of the apparatus and a second delay value corresponding to second operating conditions of the apparatus. A monitoring circuit may monitor a time taken for a first clock edge of a clock signal to propagate through the delay line. A determining circuit may determine whether operating conditions of the apparatus are acceptable in response to the time taken.

Abstract translation: 装置可以包括具有对应于装置的第一操作条件的第一延迟值和对应于装置的第二操作条件的第二延迟值的延迟线。 监视电路可以监视时钟信号的第一时钟沿所花费的时间通过延迟线传播。 确定电路可以响应于所花费的时间来确定装置的操作条件是否可接受。