公开(公告)号：US20170351617A1

公开(公告)日：2017-12-07

申请号：US15453131

申请日：2017-03-08

申请人： FUJITSU LIMITED

发明人： TAKASHI MIYOSHI

IPC分类号： G06F12/1027 ,  G06F3/06

CPC分类号： G06F12/1027 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/44521 ,  G06F9/5005 ,  G06F9/54 ,  G06F12/1009 ,  G06F15/7867 ,  G06F15/7871 ,  G06F2212/1021 ,  G06F2212/684

摘要： An information processing device, includes: a reconfigurable integrated circuit that, by being loaded with code expressing a configuration of a circuit, functions as the circuit; a memory that stores information indicating that the code is loaded into the reconfigurable integrated circuit, and resource information indicating an unused region in which circuit generation is available inside the reconfigurable integrated circuit; and a processor that searches a translation lookaside buffer (TLB) in which a virtual address associated with the code is associated with a physical address of the memory, determines, when the virtual address hits in the TLB, that the code is loaded, and generates, when the virtual address does not hit in the TLB, the circuit expressed by the code in the unused region indicated by the resource information.

公开(公告)号：US20170286582A1

公开(公告)日：2017-10-05

申请号：US15489305

申请日：2017-04-17

申请人： Altera Corporation

发明人： Junaid Asim Khan ,  Scott James Brissenden

IPC分类号： G06F17/50 ,  G06F15/78

CPC分类号： G06F17/5054 ,  G06F15/7867

摘要： Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data may be stored in a storage circuit. For the purpose of implementing the circuit design in an integrated circuit, a decoding circuit may retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of the decompression operation with the base configuration data to restore the configuration data. The restored configuration data may serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.

公开(公告)号：US20170286364A1

公开(公告)日：2017-10-05

申请号：US15629720

申请日：2017-06-21

申请人： PACT XPP TECHNOLOGIES AG

发明人： Martin Vorbach ,  Armin Nuckel

IPC分类号： G06F15/80 ,  G06F15/78 ,  G06F9/45

CPC分类号： G06F15/80 ,  G06F8/433 ,  G06F8/45 ,  G06F15/7867

摘要： An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.

公开(公告)号：US20170255252A1

公开(公告)日：2017-09-07

申请号：US15593896

申请日：2017-05-12

申请人： West Virginia University

发明人： Vinod Kulathumani ,  David W. Graham ,  Brandon David Rumberg

IPC分类号： G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3231 ,  G06F15/7867 ,  G06F17/5054 ,  H04W4/70 ,  Y02D10/12 ,  Y02D10/13

摘要： According to some embodiments, a sensor network may be provided with re-programmable and/or reconfigurable analog circuitry configured to monitor data collected by the sensor network. The re-programmable and/or reconfigurable analog circuitry may also generate a wakeup signal in response to a defined wakeup event detected by the sensor network.

公开(公告)号：US09734126B1

公开(公告)日：2017-08-15

申请号：US15289388

申请日：2016-10-10

申请人： International Business Machines Corporation

发明人： James R. Cuffney ,  Nicol Hofmann ,  Michael Klein ,  Petra Leber ,  Cédric Lichtenau ,  Silvia M. Mueller ,  Timothy J. Slegel

IPC分类号： G06F15/78 ,  G06F11/36 ,  G06F7/57

CPC分类号： G06F15/7867 ,  G06F7/57 ,  G06F11/3644 ,  G06F11/3648

摘要： A system and method for controlling post-silicon configurable instruction behavior are provided. For example, the method includes receiving data related to a compute circuit. The method also includes detecting a data pattern in the data. The method further includes determining that the data pattern is a special case that the compute circuit may handle improperly. The method also includes selecting a value from a post-silicon configurable data set based on the detected data. Further, the method includes changing a behavior of the compute circuit to produce a different output result based on the value selected from the post-silicon configurable data set.

公开(公告)号：US20170228241A1

公开(公告)日：2017-08-10

申请号：US15045057

申请日：2016-02-16

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Yong Joo KIM ,  Kyung Hee LEE ,  Chae Deok LIM

IPC分类号： G06F9/445 ,  G06F15/80

CPC分类号： G06F9/44505 ,  G06F9/5072 ,  G06F11/16 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： Provided herein are an acceleration system and a driving method thereof. The acceleration system includes a configuration memory, and a plurality of processing units which receive works from the configuration memory, perform the received works, and output results of the performed works. Each of the processing units include an n (n is an integer of three or more) number of processing elements which generate an n number of results, and each of which receives one of the works, and a select module which selects, using a majority-vote system, one of the n number of generated results and generates a selected result.

公开(公告)号：US09722614B2

公开(公告)日：2017-08-01

申请号：US14553754

申请日：2014-11-25

申请人： Qualcomm Incorporated

发明人： Mark Ian Roy Muir ,  Sami Khawam ,  Ioannis Nousias

IPC分类号： G06F13/10 ,  H03K19/177 ,  H03K19/0175 ,  G06F12/02 ,  G06F13/24 ,  G06F15/78 ,  G06F9/38

CPC分类号： H03K19/17764 ,  G06F9/3897 ,  G06F12/023 ,  G06F13/24 ,  G06F15/7867 ,  G06F2212/20 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/1776

摘要： A reconfigurable logic array(RLA) uses pipeline control methods. A do-not-end step signal is communicated to a controller in response to a backpressure condition. In response, a program executing in the RLA is suspended. Source and sink elements are arranged with respective sensors that identify back pressure conditions at interfaces. The source or sink elements communicate a do-not-end step signal to the controller. Local memory interfaces and an interrupt buffer generate similar signals in response to other internal and external conditions. The controller coordinates pipelined control signals with a global counter that issues the control signals with an end-of-step signal broadcast throughout the RLA. When a number of loop iterations is known before execution of the loop instructions, the information is shared with source and sink elements and the controller, which operate accordingly in a limited mode. At appropriate times write-enable inputs of configuration registers are disabled.

公开(公告)号：US20170212739A1

公开(公告)日：2017-07-27

申请号：US15416972

申请日：2017-01-26

申请人： ICAT LLC

发明人： Robert Catiller

IPC分类号： G06F9/45 ,  G06F9/30 ,  G06F13/40 ,  G06F9/38

CPC分类号： G06F13/4022 ,  G06F8/447 ,  G06F15/7867 ,  G06F15/7889 ,  G06F17/5027 ,  Y02D10/14 ,  Y02D10/151

摘要： An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.

公开(公告)号：US20170195173A1

公开(公告)日：2017-07-06

申请号：US14986330

申请日：2015-12-31

申请人： Amazon Technologies, Inc.

发明人： EREZ IZENBERG ,  NAFEA BSHARA ,  CHRISTOPHER PETTEY ,  CURTIS KARL OHRT

IPC分类号： H04L12/24 ,  G06F9/455 ,  G06F9/50

CPC分类号： H04L41/0806 ,  G06F9/45558 ,  G06F9/5044 ,  G06F9/5077 ,  G06F15/7867 ,  G06F15/7871 ,  G06F2009/45595 ,  H04L41/5054

摘要： A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

公开(公告)号：US20170185558A1

公开(公告)日：2017-06-29

申请号：US15455393

申请日：2017-03-10

申请人： Cypress Semiconductor Corporation

发明人： Warren S. Snyder ,  Monte Mar

IPC分类号： G06F13/40 ,  G06F13/36 ,  G06F15/78

CPC分类号： G06F13/4068 ,  G05B19/0423 ,  G05B2219/25033 ,  G06F1/08 ,  G06F1/32 ,  G06F9/44505 ,  G06F13/102 ,  G06F13/36 ,  G06F13/40 ,  G06F13/4282 ,  G06F15/7817 ,  G06F15/7867 ,  G06G7/06 ,  G11C16/10 ,  H03B5/32 ,  H03B5/364 ,  H03H19/004 ,  H03K3/012 ,  H03K3/014 ,  H03K3/02315

摘要： Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.