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公开(公告)号:US20230238875A1
公开(公告)日:2023-07-27
申请号:US17892085
申请日:2022-08-21
发明人: Ta-Yung Yang , Wei-Chuan Wu , Chih-Hao Yang , Ping-Ching Huang , Li-Wen Fang
CPC分类号: H02M1/084 , H02M1/0041 , H02M1/0043 , H02M3/158
摘要: A control circuit for controlling a stackable multiphase power converter includes: a synchronization terminal; a synchronization signal connected to the synchronization terminals of a plurality of the control circuits in parallel, wherein the synchronization signal includes a plurality of pulses to be successively counted as a count number; and a reset signal, configured to reset and initiate the count number; wherein the control circuit further comprises a phase-sequence number, wherein the control circuit enables a corresponding power stage circuit to generate a phase of the output power when the count number reaches the phase-sequence number.
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公开(公告)号:US11671030B2
公开(公告)日:2023-06-06
申请号:US17423584
申请日:2019-06-12
申请人: ABB Schweiz AG
发明人: Kai Tian , Tinho Li , Kuenfaat Yuen , Mei Liang
CPC分类号: H02M7/23 , H02M1/0064 , H02M5/293 , H02M1/0043
摘要: Voltage converter circuits including a first and second branch. The first branch is coupled between a first DC terminal and a second DC terminal and includes a first and second winding around a magnetic core. The first and second winding are coupled to an AC terminal via a common node. The second branch is coupled in parallel to the first branch between the first and second DC terminals and includes a third winding around the magnetic core. The third winding is coupled to the AC terminal such that the first and second branches convert a first voltage into a second voltage. The first, second and third windings are configured to cause magnetic flux generated by a differential mode (DM) component of a first current in the first branch and magnetic flux generated by the DM component of a second current in the second branch to enhance with each other.
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公开(公告)号:US11664717B2
公开(公告)日:2023-05-30
申请号:US17452285
申请日:2021-10-26
发明人: Richard Morrison , Phelim Bradley
CPC分类号: H02M1/0043 , H02M3/01 , H02M3/33573 , H02M1/4241
摘要: A power converter includes a transformer, a switching bridge circuit, a resonant tank circuit, an output rectifier, and a controller. The switching bridge circuit includes a plurality of switches, each switch controllable into a conduction mode and into a non-conduction mode. The controller is configured to control the plurality of switches based on a series of phase shift modulation switching cycles, each cycle comprising a control period and a delay period. During the control period, the controller causes the conduction mode of each switch of the plurality of switches to overlap a portion of each conduction mode of two other switches. During the delay period, the controller controls all of the switches into non-conduction modes overlapping in time.
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公开(公告)号:US12068682B2
公开(公告)日:2024-08-20
申请号:US17872579
申请日:2022-07-25
发明人: Sebastiano Messina , Marco Torrisi
CPC分类号: H02M1/4233 , H02M1/0043
摘要: Uncompensated upper and lower reference-currents are generated for first and second branches of a high-frequency half-bridge within an interleaved-totem-pole PFC. A first control-signal for the first branch is generated from comparison between an inductor-current and uncompensated reference-currents for the first branch, a first timing-reference is generated from the first control-signal from a number of active branches, a compensated upper reference-current is generated for the second branch by adding a first compensation-current to the uncompensated upper reference-current for the second branch, a compensated lower reference-current is generated for the second branch by subtracting the first compensation-current from the uncompensated lower reference-current for the second branch, a second control-signal is generated for the second branch from the compensated reference-currents for the second branch, a first timing-difference is generated from a phase-difference between the first and second control-signals, and the first compensation-current is generated from a difference between the first timing-reference and timing-difference.
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公开(公告)号:US12068674B2
公开(公告)日:2024-08-20
申请号:US17588402
申请日:2022-01-31
发明人: Haijun Yang , Zengyi Lu , Lijun Zhou
CPC分类号: H02M1/0064 , H01F27/24 , H01F27/306 , H01F27/38 , H02M3/1586 , H01F37/00 , H02M1/0043 , H02M3/01 , H02M3/335
摘要: An integrated inductor and a power conversion module including the integrated inductor are provided. The integrated inductor includes a magnetic core, the magnetic core including two cover plates, two side columns and two central columns between the two side columns, and two windings wound around the two central columns respectively, forming two inductors. Each operating current flowing through the two windings includes a corresponding high-frequency current component, a phase difference between the high-frequency current components of the operating currents flowing through the two windings is 180 degrees.
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36.
公开(公告)号:US20240248522A1
公开(公告)日:2024-07-25
申请号:US18307375
申请日:2023-04-26
发明人: Kum Kang Huh , Hridya Ittamveettil , Luis J. Garces , Rajib Datta , Di Pan , Yukai Wang
CPC分类号: G06F1/30 , B64D41/00 , H02M1/0043 , H02M7/797
摘要: A multilevel power converter includes a plurality of switches, a first DC link capacitor, a second DC link capacitor, and one or more processors configured to: generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme; modify the pulse width modulated pulse pattern to render a modified pulse pattern; and cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance voltages at the first DC link capacitor and the second DC link capacitor.
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37.
公开(公告)号:US12040698B2
公开(公告)日:2024-07-16
申请号:US17691798
申请日:2022-03-10
申请人: ABB Schweiz AG
发明人: Esa-kai Paatero , Nicola Notari
CPC分类号: H02M1/4233 , H02J9/061 , H02J9/062 , H02M1/0067 , H02M7/217 , H02M7/4833 , H02M7/487 , H02M7/537 , H02M1/0043
摘要: A system and method for an uninterruptible power supply (UPS) includes a first converter assembly, a second converter assembly, a third converter assembly, a first controlled device configured for disconnecting at least two converters of the first converter assembly from and AC source, and a second controlled device configured for connecting at least two of the first converters together, and comprising the step of: opening the first controlled device and closing the second controlled device such that the first converter assembly transfers energy between split DC link halves to maintain voltage regulation of the DC link with respect to the midpoint reference.
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公开(公告)号:US12021454B2
公开(公告)日:2024-06-25
申请号:US17730878
申请日:2022-04-27
CPC分类号: H02M3/1586 , H02M1/0009 , H02M1/08 , H02M1/0043
摘要: A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.
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公开(公告)号:US20240195322A1
公开(公告)日:2024-06-13
申请号:US18076996
申请日:2022-12-07
申请人: Dell Products L.P.
发明人: Shiguo Luo , Guangyong Zhu , Lei Wang , Feng-Yu Wu
CPC分类号: H02M7/537 , G06F1/26 , H02M1/0043
摘要: A voltage regulator includes a first portion with a first converter phase and a second portion with second and third converter phases, and a compensation inductor. The first converter phase receives an input voltage and provides an output voltage through a first inductor. The second converter phase receives the input voltage and provides the output voltage through a first primary winding of a first coupled inductor. The first coupled inductor includes a first secondary winding magnetically coupled to the first primary winding. The third converter phase receives the input voltage and provides the output voltage through a second primary winding of a second coupled inductor. The second coupled inductor includes a second secondary winding magnetically coupled to the second primary winding. The compensation inductor, first secondary winding, and of the second secondary winding are coupled in series between a ground plane.
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公开(公告)号:US12009690B2
公开(公告)日:2024-06-11
申请号:US18344725
申请日:2023-06-29
申请人: Nextracker LLC
IPC分类号: H02M3/158 , G05F1/56 , G05F1/59 , G05F1/595 , H02J7/35 , H02M1/088 , H02M3/06 , H02S20/32 , G05F1/70 , H02M1/00 , H02M3/00 , H02M3/335 , H02P27/08 , H02S40/32 , H02S40/38
CPC分类号: H02J7/35 , H02M3/1582 , H02S20/32 , G05F1/56 , G05F1/59 , G05F1/595 , G05F1/70 , H02M1/0043 , H02M1/088 , H02M3/01 , H02M3/06 , H02M3/158 , H02M3/33571 , H02P27/08 , H02S40/32 , H02S40/38
摘要: A power converter converts a medium-voltage output from a solar module to an appropriate voltage to power a solar tracker system. The power converter includes a voltage divider having at least two legs, a first semiconductor switch subassembly coupled in parallel with a first leg of the voltage divider, and a second semiconductor switch subassembly coupled in parallel with a second leg of the voltage divider. The power converter may be a unidirectional or a bidirectional power converter. In implementations, the signals for driving the semiconductor switches of the first and second semiconductor switch subassemblies may be shifted out of phase from each other. In implementations, if the bus voltages to the semiconductor switches are not balanced, the pulse width of the driving signal of the semiconductor switch supplied with the higher bus voltage is decreased for at least one cycle.
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