公开(公告)号：US07379010B2

公开(公告)日：2008-05-27

申请号：US11553464

申请日：2006-10-26

Applicant: John Philip Tero

Inventor： John Philip Tero

IPC: H03M1/12

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Abstract translation: 通过比较器阵列中的比较器输出的内插，ADC精度增加1位，从而提高精度，而不会显着增加功耗和尺寸。 具体地，模数转换器包括二进制转换器和比较器阵列，其包括多个比较器块，每个块具有主比较器和内插比较器。 内插比较器将来自主比较器的输出信号与来自多个块的另一块的主比较器的负输出信号进行比较，以生成最低有效位。 耦合到阵列的二进制转换器将阵列输出转换为二进制代码。

公开(公告)号：US20070263732A1

公开(公告)日：2007-11-15

申请号：US11803392

申请日：2007-05-14

Applicant: Shigenori Yamauchi ,  Takamoto Watanabe

Inventor： Shigenori Yamauchi ,  Takamoto Watanabe

IPC: H04B14/04

CPC classification number: H03M1/206 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

Abstract: The digitization apparatus includes, as a main scale, a pulse delay circuit constituted by a plurality of delay units connected in series or in ring form, a latch/encoder, a circulation number counter, and a latch circuit, and includes, as a vernier, a reverse timing extraction circuit detecting a reverse timing at which any one of the delay units has reversed, and an interpolation circuit. The main scale digitizes a time interval between two successive measurement signals in a resolution equal to a delay time per one delay unit. The vernier digitizes a time difference between a measurement timing indicated by the measurement signal and the reverse timing in a resolution equal to 1/M (M being an integer not smaller than 2). The interpolation circuit includes two delay lines each constituted by a plurality of delay units connected in series or in ring form.

Abstract translation: 数字化装置包括作为主要尺度的由串联或环形连接的多个延迟单元，锁存/编码器，循环号计数器和锁存电路构成的脉冲延迟电路，并且包括作为游标 检测任一个延迟单元已经反转的反向定时的反向定时提取电路和内插电路。 主比例数字化两个连续的测量信号之间的时间间隔，其分辨率等于每个延迟单元的延迟时间。 游标数字化测量信号所示的测量定时与反向定时之间的时差，其分辨率等于1 / M（M为不小于2的整数）。 插补电路包括两个延迟线，每条延迟线由串联或环形连接的多个延迟单元构成。

公开(公告)号：US20070096971A1

公开(公告)日：2007-05-03

申请号：US11553464

申请日：2006-10-26

Applicant: John Tero

Inventor： John Tero

IPC: H03M1/12

CPC classification number: H03M1/206 ,  H03M1/361

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increase accuracy without significant increasing power consumption and size.

Abstract translation: 通过比较器阵列中的比较器输出的内插，ADC精度增加1位，从而提高精度，而不会显着增加功耗和尺寸。

公开(公告)号：US20040239546A1

公开(公告)日：2004-12-02

申请号：US10854297

申请日：2004-05-26

Inventor： Takamoto Watanabe ,  Takayuki Torigoe ,  Koji Adumi ,  Hidetoshi Yamauchi

IPC: H03M001/60

CPC classification number: H03M1/206 ,  G04F10/005 ,  H03M1/502

Abstract: An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.

Abstract translation: 一种A / D转换器，用于通过模拟输入信号Vin驱动形成脉冲延迟电路的多个延迟单元，并且将预定时间脉冲信号通过脉冲信号的延迟单元的数量化，并设置多个延迟单元 用于A / D转换的脉冲位置数字化单元，并且通过由不同输入定时具有不同反相电平（开关阈值电平）的反相器组成的反相器组将延迟脉冲从脉冲延迟电路的延迟单元输入到脉冲位置数字化单元。 由脉冲位置数字化单元获得的数字数据由加法器相加。

公开(公告)号：US20040135715A1

公开(公告)日：2004-07-15

申请号：US10604527

申请日：2003-07-29

Inventor： Tai-Haur Kuo ,  Kuo-Hsin Chen ,  Jyh-Fong Lin ,  Hsin-Chieh Lin

IPC: H03M001/34

CPC classification number: H03M1/1023 ,  H03M1/0682 ,  H03M1/1004 ,  H03M1/206 ,  H03M1/365

Abstract: An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Abstract translation: 模拟数字数据转换器将输入信号转换成相应的数字信号。 数据转换器包括以隔行方式布置的两组比较单元，以交替地分析输入信号，产生对应于比较输入信号和参考信号的结果的数字信号。 每个比较单元具有正输出和负输出，并且数字信号以差分方式由负输出和比较单元的正输出产生。 当一组的比较单元正在执行自动归零时，另一组的比较单元执行数据转换以产生相应的数字信号。

公开(公告)号：US20020021232A1

公开(公告)日：2002-02-21

申请号：US09905876

申请日：2001-07-17

Inventor： Michiharu Shoji ,  Nobutsune Kobayashi

IPC: H03M001/22

CPC classification number: H03M1/206 ,  G01P3/481 ,  H03M1/303

Abstract: A digital encoder control method of a digital control apparatus having a driving unit, a frequency signal generating unit for generating a pulse signal of a frequency according to a driving velocity of a driven member which is driven by the driving unit, an edge detecting unit for detecting a rising-up edge and a falling-down edge of the pulse signal, and a period data detecting unit for counting period data between edges detected by the edge detecting unit, wherein each time the edges are detected by the edge detecting unit, the period data between the same edges as the detected edges is outputted as control velocity data of the driving unit.

Abstract translation: 一种具有驱动单元的数字控制装置的数字编码器控制方法，频率信号发生单元，用于根据由驱动单元驱动的从动构件的驱动速度产生频率的脉冲信号;边缘检测单元， 检测脉冲信号的上升沿和下降沿;以及周期数据检测单元，用于对由边缘检测单元检测到的边缘之间的周期数据进行计数，其中每次由边缘检测单元检测到边缘时， 输出与检测出的边缘相同的边缘之间的周期数据作为驱动单元的控制速度数据。

公开(公告)号：US06175520B1

公开(公告)日：2001-01-16

申请号：US08866094

申请日：1997-05-30

Applicant: T. Damodar Reddy ,  Abhijit Ray

Inventor： T. Damodar Reddy ,  Abhijit Ray

IPC: G11C1134

CPC classification number: H03M1/007 ,  H03M1/206 ,  H03M1/365

Abstract: A flash EPROM device (100) is disclosed. During a programming operation, a primary programming voltage circuit (116) drives I/O lines (110) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (118) are located remotely from the primary programming voltage circuit (116) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (116) and the secondary programming voltage circuits (118).

Abstract translation: 闪存EPROM设备（100）被公开。 在编程操作期间，主编程电压电路（116）根据输入数据值将I / O线（110）驱动到编程电压（Vp）。 第二编程电压电路（118）远离主编程电压电路（116）定位，并且响应于I / O线上的电压电平进一步将I / O线驱动到Vp。 这种布置减少了对主编程电压电路（116）和次级编程电压电路（118）之间的阻抗的负载线响应的影响。

公开(公告)号：US5920275A

公开(公告)日：1999-07-06

申请号：US925631

申请日：1997-09-09

Applicant: Richard K. Hester

Inventor： Richard K. Hester

IPC: H03M1/20 ,  H03M1/46 ,  H03M1/14

CPC classification number: H03M1/206 ,  H03M1/468

Abstract: A charge redistribution analog-to-digital converter uses an interpolative comparator to determine multiple bits in a single comparator decision cycle. The result is a speed improvement in the conversion period with little or no increase in power dissipation.

Abstract translation: 电荷再分配模数转换器使用内插比较器来确定单个比较器决策周期中的多个比特。 结果是转换周期的速度提高，功耗很少或没有增加。

公开(公告)号：US5798725A

公开(公告)日：1998-08-25

申请号：US743853

申请日：1996-11-05

Applicant: Kouji Okada

Inventor： Kouji Okada

IPC: G01R19/165 ,  H03K5/08 ,  H03K5/24 ,  H03M1/14 ,  H03M1/20 ,  H03M1/34 ,  H03M1/36 ,  H03M1/12

CPC classification number: H03M1/206 ,  H03K5/249 ,  H03M1/365

Abstract: An improved method and apparatus related to a comparator particularly suited for use in an A/D converter so as to obtain a high resolution, which results in a reduced circuit area and operates with low power consumption. To compare an analog input voltage and reference voltages, the comparator includes chopper type comparators for producing comparison voltages and determination signals, and includes a determination circuit for producing one or more additional determination signals. The chopper type comparators may further include amplifiers and determination circuits.

Abstract translation: 一种与比较器相关的改进的方法和装置，特别适用于A / D转换器以获得高分辨率，这导致电路面积减小并且以低功耗运行。 为了比较模拟输入电压和参考电压，比较器包括用于产生比较电压和确定信号的斩波器类型比较器，并且包括用于产生一个或多个附加确定信号的确定电路。 斩波器类型比较器还可以包括放大器和确定电路。

公开(公告)号：US4973959A

公开(公告)日：1990-11-27

申请号：US196200

申请日：1988-05-04

Applicant: Katsuo Kobari ,  Yoshitaka Takekoshi ,  Mitsuyuki Taniguchi

Inventor： Katsuo Kobari ,  Yoshitaka Takekoshi ,  Mitsuyuki Taniguchi

IPC: G01D5/245 ,  G01D5/244 ,  H03M1/20 ,  H03M1/30

CPC classification number: H03M1/206 ,  G01D5/244 ,  G01D5/24404 ,  G01D5/24476 ,  H03M1/303

Abstract: A digital pulse circuit receives parallel N digital signals, assuming N is an even integer equal to or greater than 4, the levels of the signals inverted every time a constant quantity of change in an objective quantity to be measured occurs, any phase differences between the successive signals of the signals about 1/N of the constant quantity; has a logic circuit which enables only two signals which can change state in due process corresponding to the next change of the objective quantity to be measured, to enter the next stage; and synchronizes each of the N digital signals by a clock pulse, to make any phase difference among the N digital signals equal to or more than a predetermined phase difference, and the remove the influence of noise superposed on the digital signals (FIG. 10). In addition, a digital pulse circuit mentioned above; synchronizes each of the N digital signals by a clock pulse; and further synchronizes each of the synchronized signals by the clock pulse, once again; and enables only two signals which can change their states in due process corresponding to the next change of the objective quantity to be measured, among the signals synchronized once, to enter the next stage; and when two of the once-synchronized signals have changed at the same time, maintains the two once-synchronized signals so as not to be synchronized twice, until one of the two signals returns to the state just before the change (FIG. 14).

Abstract translation: PCT No.PCT / JP87 / 00666 Sec。 371日期：1988年5月4日 102（e）日期1988年5月4日PCT提交1987年9月9日PCT公布。 第WO88 / 02104号公报 日期：1988年3月24日。数字脉冲电路接收并行N个数字信号，假设N是等于或大于4的偶数整数，每次待测量的目标量的恒定变化量反转信号的电平 发生信号的连续信号之间的任何相位差约为常数量的1 / N; 具有逻辑电路，其仅使得能够根据待测量的目标量的下一次变化而适当地改变状态的两个信号进入下一个阶段; 并且通过时钟脉冲使每个N个数字信号同步，使N个数字信号之间的任何相位差等于或大于预定相位差，并消除叠加在数字信号上的噪声的影响（图10） 。 另外，上述数字脉冲电路; 通过时钟脉冲使每个N个数字信号同步; 并再次同步每个同步信号的时钟脉冲; 并且在一次同步的信号中仅使两个信号能够在适当的处理中改变与待测量的目标量的下一个变化相对应的状态，以进入下一个阶段; 并且当两个同步信号中的两个同时改变时，保持两个一次同步的信号，以便不被同步两次，直到两个信号中的一个返回到刚刚改变之前的状态（图14） 。