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1.发明申请Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US20100237923A1
公开(公告)日：2010-09-23
申请号：US12661156
申请日：2010-03-11
IPC分类号： H03H11/26 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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2.发明申请Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof 有权用于控制脉冲延迟电路的延迟时间及其脉冲延迟电路的方法公开(公告)号：US20090135040A1
公开(公告)日：2009-05-28
申请号：US12292761
申请日：2008-11-25
CPC分类号： H03K5/133
摘要： An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.
摘要翻译： 配置延迟单元的逆变器电路是所谓的CMOS晶体管，其包括PMOS晶体管和NMOS晶体管，其中相应的栅极互连并且相应的漏极互连。 NMOS晶体管的源极和背栅极连接到地。 PMOS晶体管的源极连接到正极驱动端子并由模拟输入信号控制。 PMOS晶体管的背栅极连接到控制端子并由控制信号控制。
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3.发明授权Recirculating delay line digital pulse generator having high control proportionality 失效具有高控制比例的再循环延迟线数字脉冲发生器
公开(公告)号：US5525939A
公开(公告)日：1996-06-11
申请号：US501269
申请日：1995-07-12
CPC分类号： H03K3/0315 , H03K5/135
摘要： In a digital control pulse generator including a ring oscillator composed of multiple inversion circuits connected in a ring for circulating a pulse, a counter and selectors which turn data of a flip-flop to high when a counted value of the pulse from a terminal of the ring oscillator becomes a value corresponding to ten high order bits of control data, a pulse selector for taking out a clock of the flip-flop from the inversion circuit at the position specified by four bit control data and a delay line and logical product circuit which turn an output signal of the system to a high level for a predetermined time when the output of the flip-flop turns high, a register and adder accumulate the four low order bits of the control data every time the output signal turns high to update the data four bit data. As a result, the ring oscillator may be continuously operated and an oscillation cycle proportional to the control data may be set.
摘要翻译： 在包括环形振荡器的数字控制脉冲发生器中，所述环形振荡器由连接在环中以循环脉冲的多个反相电路组成，计数器和选择器将触发器的数据值从 环形振荡器成为对应于控制数据的十个高位位的值，用于在由四位控制数据指定的位置处的反相电路中取出触发器的时钟的脉冲选择器和延迟线以及逻辑积电路， 当触发器的输出变为高电平时，将系统的输出信号转换到高电平达预定时间，寄存器和加法器在每当输出信号变为高电平时累积控制数据的四个低位，以更新 数据四位数据。 结果，可以连续地操作环形振荡器，并且可以设置与控制数据成比例的振荡周期。
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公开(公告)号：US5477196A
公开(公告)日：1995-12-19
申请号：US362648
申请日：1994-12-23
IPC分类号： G01R25/00 , G01R25/08 , G01R29/02 , H03K3/03 , H03K3/354 , H03K5/00 , H03K5/135 , H03K5/26 , H03L7/06 , H03L7/085 , H03B27/00 , H03L7/083 , H03L7/18
CPC分类号： H03K3/0315 , H03K5/135
摘要： In a device for encoding a pulse phase difference or controlling an oscillation frequency based on delayed signals sequentially output by a delay circuit, the encoding of a pulse phase difference or the oscillation control can be simultaneously performed using a single delay device. There is provided a frequency converter including a ring oscillator consisting of inverting circuits interconnected in the form of a ring, a pulse phase difference encoding circuit for encoding the cycle of a reference signal into a binary digital value based on a pulse output by the ring oscillator, an arithmetic circuit for multiplying or dividing the binary digital value by a predetermined value to generate control data and a digitally controlled oscillation circuit for generating a pulse signal in a cycle in accordance with the control data based on the pulse output by the ring oscillator, the ring oscillator being shared by the encoding circuit and oscillation circuit. This makes the time resolution of the encoding and oscillation circuits constant, thereby allowing accurate frequency conversion.
摘要翻译： 在根据由延迟电路顺序输出的延迟信号对脉冲相位差进行编码或控制振荡频率的装置中，可以使用单个延迟装置同时进行脉冲相位差的编码或振荡控制。 提供了一种变频器，包括由环形互连的反相电路构成的环形振荡器，用于基于环形振荡器输出的脉冲将参考信号的周期编码为二进制数字值的脉冲相位差编码电路 ，用于将二进制数字值乘以预定值以产生控制数据的运算电路和用于根据由环形振荡器输出的脉冲输出的控制数据在一个周期内产生脉冲信号的数字控制振荡电路， 环形振荡器由编码电路和振荡电路共享。 这使得编码和振荡电路的时间分辨率恒定，从而允许精确的频率转换。
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公开(公告)号：US6082196A
公开(公告)日：2000-07-04
申请号：US845895
申请日：1997-04-28
IPC分类号： G01D5/24 , G01P15/125 , G01P15/13 , G01P15/14
CPC分类号： G01P15/131 , G01P15/125
摘要： A physical quantity detecting is capable of easily adjusting sensitivity and an offset of a detected output without being increased in size. In a signal processor for driving a sensor element in which fixed electrodes are disposed on both sides of a movable electrode displaced in response to acceleration, a signal generator generates PWM signals PA and PB in which an invalid control period during which the fixed electrodes are both deenergized only during a period corresponding to data M3 stored in a memory, is, at a predetermined ratio, inserted into a valid control period during which the fixed electrodes are alternately energized and their energization ratio is controlled so that the movable electrode is placed in position. Since the sensitivity of the sensor element to the acceleration changes according to the length of the invalid control period which does not contribute to control of the position of the movable electrode, its sensitivity can be easily adjusted by simply changing the value set in the memory.
摘要翻译： 物理量检测能够容易地调节灵敏度和检测输出的偏移而不增大尺寸。 在用于驱动传感器元件的信号处理器中，其中固定电极设置在响应于加速度而移位的可移动电极的两侧，信号发生器产生PWM信号PA和PB，其中固定电极均为无效控制周期 仅在对应于存储在存储器中的数据M3的周期期间被断电，以预定比例插入到固定电极交替通电的有效控制周期中，并且控制其通电率，使得可动电极位于 。 由于传感器元件对加速度的灵敏度根据无效控制周期的长度而变化，这对于可移动电极的位置的控制无助于其灵敏度，因此可以通过简单地改变在存储器中设置的值来容易地调整灵敏度。
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6.发明授权Programmable delay line programmable delay circuit and digital controlled oscillator 失效可编程延迟线可编程延迟电路和数字控制振荡器
公开(公告)号：US5465076A
公开(公告)日：1995-11-07
申请号：US111488
申请日：1993-08-25
CPC分类号： H03K5/135 , H03K3/0315 , H03L7/0996 , H03L7/0997
摘要： A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times. The oscillator of the programmable delay apparatus can be controlled by a control signal. Addition of a feedback circuit for supplying the delay signal from the delay line as the control signal to the oscillator of the programmable delay apparatus provides a digital controlled oscillator.
摘要翻译： 可编程延迟线包括串联连接的多个延迟级，每个延迟级包括：用于传递输入信号的基本路径; 用于以预定的延迟时间传递输入信号的延迟路径; 以及选择器，用于选择基本路径或延迟路径以根据外部输入的数字数据传递输入信号，其中通过基本路径的输入信号和通过多个延迟级中的延迟路径的时间差为 UD.2n（n = 0,1,2，...），UD为单位延迟时间。 一种可编程延迟装置包括：振荡器和计数器，其根据控制数据的高位数据确定粗延迟时间;以及可编程延迟线，其根据控制数据的较低位数据确定精细延迟时间 完成粗延时后获得总延迟时间。 该计数器提供广泛的可用延迟时间。 可编程延迟装置的振荡器可以通过控制信号来控制。 添加用于将来自延迟线的延迟信号作为控制信号提供给可编程延迟装置的振荡器的反馈电路提供数字控制振荡器。
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公开(公告)号：US5416444A
公开(公告)日：1995-05-16
申请号：US177682
申请日：1994-01-05
CPC分类号： H03K3/0315 , G01R25/08 , H03K5/131 , Y10S331/03
摘要： A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal. A control signal inputting arrangement serves to input the second control signal to the second start inverting circuit during an interval from a first moment at which the first control signal is inputted into the first start inverting circuit and the first start inverting circuit starts the inverting operation to a second moment at which a pulse edge initially generated by the start of the inverting operation of the first start inverting circuit and travelling while being sequentially inverted by the inverting circuits enters the second start inverting circuit.
摘要翻译： 用于循环两种类型的脉冲边缘的环形振荡器包括以环形连接的偶数反相电路。 每个反相电路用于反转输入信号并输出输入信号的反相。 反相电路中的一个是第一启动反相电路，其响应于从外部输入施加的第一控制信号开始反相输入信号的操作。 除了第一启动反相电路和紧接在第一启动反相电路之后的反相电路之一的反相电路中的一个是响应于第二控制信号开始反相输入信号的操作的第二启动反相电路。 控制信号输入装置用于在从第一控制信号被输入到第一起动反向电路的第一时刻开始间隔期间将第二控制信号输入到第二启动反转电路，并且第一启动反相电路开始转换操作 第二时刻，由第一起动反转电路的反相操作开始初始产生的脉冲沿并且由反相电路顺序反转的第二时刻进入第二启动反相电路。
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公开(公告)号：US5708395A
公开(公告)日：1998-01-13
申请号：US800236
申请日：1997-02-12
CPC分类号： H03L7/0991
摘要： A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference signal PREF multiplied by sixteen (32/2) is generated by the digital oscillation circuit.
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9.发明授权Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US08307320B2
公开(公告)日：2012-11-06
申请号：US12661156
申请日：2010-03-11
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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公开(公告)号：US07825696B2
公开(公告)日：2010-11-02
申请号：US12653664
申请日：2009-12-16
IPC分类号： H03K19/00
CPC分类号： H03K3/0315
摘要： The even-number-stage pulse delay includes a ring delay line constituted of an even number of inverter circuits connected in a ring around which main edge and a reset edge circulate together. The even-number-stage pulse delay is provided with an operation monitoring section configured to detect whether or not the main and reset edges are circulating around the ring delay line.
摘要翻译： 偶数级脉冲延迟包括由连续在主边缘和复位边缘一起循环的环中的偶数个反相器电路构成的环形延迟线。 偶数阶段脉冲延迟设置有操作监视部分，其被配置为检测主和复位边沿是否在环延迟线周围循环。
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