公开(公告)号：US20100066450A1

公开(公告)日：2010-03-18

申请号：US12524525

申请日：2008-02-11

申请人： Robert E. Palmer ,  John W. Poulton

发明人： Robert E. Palmer ,  John W. Poulton

IPC分类号： H03F3/45 ,  H03K3/01

CPC分类号： H04L25/063 ,  H03F3/45179 ,  H03F2203/45008 ,  H03F2203/45306 ,  H03F2203/45588 ,  H04L7/046 ,  H04L25/0278

摘要： A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations.

摘要翻译： 低压差分通信系统包括低频和可编程摆幅电压模式发射机，通过差分信道将低电压差分信号传送到接收机。 接收机采用两个输入晶体管，每个输入晶体管采用共栅配置，以恢复低电压差分信号。 接收器中的电流源偏置输入晶体管，使得它们的源电压在标称偏置在差分信号的共模电压下，并且它们的栅源电压在共模电压波动下保持基本恒定。

公开(公告)号：US07668275B2

公开(公告)日：2010-02-23

申请号：US11109055

申请日：2005-04-19

申请人： Jens-Uwe Jürgensen ,  Richard Stirling-Gallacher

发明人： Jens-Uwe Jürgensen ,  Richard Stirling-Gallacher

IPC分类号： H04L7/00 ,  H04J3/06

CPC分类号： H04J3/0602 ,  H04B1/7183 ,  H04L7/046

摘要： A frame synchronization is proposed for a multi-band communication system, wherein a data signal exchanged between a transmitter and a receiver is organized in system frames having a preamble section which contains a frame synchronization section that is composed of a number of symbol frames, each of which is in turn composed of a defined number of slots, whereby each slot corresponds to an individual transmission frequency band. The method comprises steps for transmitting the data signal containing a synchronization signal in one or more slots of every other symbol frame of the frame synchronization section, processing only data signal components selected from transmission frequency bands required for the synchronization signal transmission, and subtracting the processed data signal from its shifted copy, whereby the copy is shifted by one symbol frame.

摘要翻译： 针对多频带通信系统提出了帧同步，其中在发射机和接收机之间交换的数据信号被组织在具有前导码部分的系统帧中，该前同步码段包含由多个符号帧组成的帧同步部分 其又由限定数量的时隙组成，由此每个时隙对应于单独的传输频带。 该方法包括以下步骤，用于在帧同步部分的每隔一个符号帧的一个或多个时隙中发送包含同步信号的数据信号，仅处理从同步信号传输所需的传输频带中选择的数据信号分量， 数据信号从其偏移的副本，从而复制被移位一个符号帧。

公开(公告)号：US20100039156A1

公开(公告)日：2010-02-18

申请号：US12530549

申请日：2008-02-27

申请人： Kouichi Yamaguchi

发明人： Kouichi Yamaguchi

IPC分类号： G06F1/04

CPC分类号： H04L7/046 ,  G09G3/2096 ,  G09G5/008 ,  H03L7/06 ,  H04L7/033 ,  H04L7/10

摘要： A clockless transmission system includes display controller 101 and display driver 106. Display controller 101 includes data transmission circuit 102 configured to output general data obtained by multiplexing a clock by coding serialized pixel data for each pixel data during a data communication interval and also to output a predetermined control signal during a blanking interval. Display driver 106 includes clock and data recovery circuit 107 configured to output the pixel data from the general data transferred from the display controller and to increase a loop gain of a feedback loop in clock recovery such that the loop gain is larger than that when the general data is received, according to control data of the control signal, to recover and output a clock, and display driving circuit 109 configured to output a signal for driving a display based on the pixel data and the recovered clock.

摘要翻译： 无时钟传输系统包括显示控制器101和显示驱动器106.显示控制器101包括数据发送电路102，其被配置为输出通过在数据通信间隔期间对每个像素数据编码串行化像素数据来复用时钟而获得的一般数据，并且还输出 在消隐间隔期间预定的控制信号。 显示驱动器106包括时钟和数据恢复电路107，其被配置为从显示控制器传送的一般数据输出像素数据，并且增加在时钟恢复中的反馈回路的环路增益，使得环路增益大于当一般 根据控制信号的控制数据接收数据以恢复和输出时钟，并且显示驱动电路109被配置为基于像素数据和恢复的时钟输出用于驱动显示的信号。

公开(公告)号：US07636410B2

公开(公告)日：2009-12-22

申请号：US10360436

申请日：2003-02-07

申请人： Geert Maria Marcel Vandensande

发明人： Geert Maria Marcel Vandensande

IPC分类号： H04L7/00

CPC分类号： H04L7/046 ,  G06F13/40 ,  H04L7/0331 ,  H04L12/04

摘要： The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.

摘要翻译： 本发明涉及一种在协议处理程序中处理数字信号的方法，协议处理程序是耦合到多路复用总线的模块的一部分。 该方法包括检测数字信号的占空比，以及修改所述数字信号，使得修改的信号包含相同的数据，但占空比约为50％。

公开(公告)号：US20090292434A1

公开(公告)日：2009-11-26

申请号：US12373569

申请日：2007-07-13

申请人： Markus Bläser

发明人： Markus Bläser

IPC分类号： G06F19/00 ,  B60T8/88

CPC分类号： B60T8/885 ,  B60T2260/08 ,  B60T2270/406 ,  B60T2270/413 ,  H04J3/0664 ,  H04L7/046 ,  H04L7/10 ,  H04L12/40026

摘要： The invention relates to a method for synchronising components of a motor vehicle brake system with an electronic main control device with a main timer associated therewith, at least one sub-control device, which is subordinate to the main control device, with a timer associated therewith, wherein the main control device communicates with the at least one sub-control device in cycles, wherein, furthermore, the main control device and the at least one sub-control device in each case increment a cycle counter associated therewith. In this connection the main control device sends synchronising data which comprise a value of the cycle counter of the main control device to the at least one sub-control device, and the at least one sub-control device receives these synchronising data and sets its cycle counter to the received value of the cycle counter of the main control device if the received value of the cycle counter of the main control device differs from the value of the cycle counter of the sub-control device.

摘要翻译： 本发明涉及一种用于使机动车辆制动系统的组件与具有与其相关联的主定时器的电子主控制装置同步的方法，至少一个副控制装置，其隶属于主控制装置，其中定时器与其相关联 其中，所述主控制装置以周期方式与所述至少一个副控制装置进行通信，此外，主控制装置和所述至少一个副控制装置在每种情况下增加与其相关联的循环计数器。 在这方面，主控制装置将包括主控装置的循环计数器的值的同步数据发送到至少一个子控制装置，并且至少一个子控制装置接收这些同步数据并设置其周期 如果主控制装置的循环计数器的接收值与副控制装置的循环计数器的值不同，则与主控装置的循环计数器的接收值相反。

公开(公告)号：US20090231045A1

公开(公告)日：2009-09-17

申请号：US12475903

申请日：2009-06-01

申请人： Chih-Ming LIAO ,  Chia-Chang Chen ,  Min-Yi Chen

发明人： Chih-Ming LIAO ,  Chia-Chang Chen ,  Min-Yi Chen

IPC分类号： H03L7/099

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L7/181 ,  H04L7/0004 ,  H04L7/033 ,  H04L7/046

摘要： A frequency-locking device including a digitally-controlled oscillator (DCO) and a comparing unit is disclosed. The DCO is used for generating an output frequency signal. The comparing unit receives a Keep Alive signal or a start of a frame (SOF) from a universal serial bus (USB) and the output frequency signal, and compares the Keep Alive signal or the start of a frame (SOF) with the output frequency signal to generate a calibration signal. Then, the DCO adjusts the frequency of the output frequency signal according to the calibration signal to meet the USB specification for data communication.

摘要翻译： 公开了一种包括数字控制振荡器（DCO）和比较单元的频率锁定装置。 DCO用于产生输出频率信号。 比较单元从通用串行总线（USB）和输出频率信号接收保持激活信号或帧起始（SOF），并将保持激活信号或帧起始（SOF）与输出频率进行比较 信号产生校准信号。 然后，DCO根据校准信号调整输出频率信号的频率，以符合USB规范进行数据通信。

公开(公告)号：US20090129505A1

公开(公告)日：2009-05-21

申请号：US12247871

申请日：2008-10-08

申请人： Frederick A. Ware ,  Robert E. Palmer ,  John Poulton

发明人： Frederick A. Ware ,  Robert E. Palmer ,  John Poulton

IPC分类号： H04L27/00

CPC分类号： H04L7/0337 ,  G06F13/4243 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/2227 ,  H03L7/06 ,  H04L7/0008 ,  H04L7/046 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.

摘要翻译： 为使用固定时钟速率接口的部分速率传输模式提供了系统和方法。 在部分速率模式下，每个数据位连续传输两次或更多次。 接收机使用不进行相位调整的全局时钟来检测复制的传入位。 结果，当系统锁定到从发射机接收的数据的相位时，接收机系统可以以部分数据速率接收数据。

公开(公告)号：US20090123160A1

公开(公告)日：2009-05-14

申请号：US12349914

申请日：2009-01-07

申请人： Yusuke YAJIMA ,  Tohru KAZAWA ,  Yoshihiro ASHI

发明人： Yusuke YAJIMA ,  Tohru KAZAWA ,  Yoshihiro ASHI

IPC分类号： H04L7/00 ,  H04L27/06 ,  H04B10/00

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0004 ,  H04L7/046

摘要： A bit synchronization circuit comprising an initial phase determining unit for rapidly determining, during a period of receiving a preamble of burst data, a clock with a phase synchronized with received burst data from among multi-phase clocks having the same frequency as an internal reference clock and a phase tracking unit for modifying the synchronized phase clock responsive to phase variation of received data during a period of receiving a payload of burst data by taking the synchronized phase clock determined by the initial phase determining unit as an initial phase. The bit synchronization circuit retimes burst data with a data retiming clock having a predetermined phase relation with the synchronized phase clock and outputs the burst data in synchronization with the internal reference clock.

摘要翻译： 一种位同步电路，包括初始相位确定单元，用于在从脉冲串数据的前导码接收周期内快速确定具有与内部参考时钟相同频率的多相位时钟中的接收脉冲串数据同步的时钟 以及相位跟踪单元，用于通过将由初始相位确定单元确定的同步相位时钟作为初始相位，在接收到突发数据的有效载荷的周期期间响应于接收数据的相位变化来修正同步相位时钟。 位同步电路使用具有与同步相位时钟具有预定相位关系的数据重新定时时钟重新匹配突发数据，并且与内部参考时钟同步输出脉冲串数据。

公开(公告)号：US20090106460A1

公开(公告)日：2009-04-23

申请号：US12295051

申请日：2007-02-20

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Noriaki Takeda ,  Toru Iwata ,  Takaharu Yoshida ,  Yoshiyuki Saito

IPC分类号： G06F3/00

CPC分类号： H04L7/10 ,  G06F1/12 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/044 ,  H04L7/046

摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section 41 of receiving transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section 45 of generating a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section of transmitting the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.

摘要翻译： 本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。 一种向主机终端发送/接收数据的可移动存储装置，包括：用于在主机终端和可移动存储装置之间发送/接收数据的接收发送/接收时钟的时钟接收部分41， 主机终端; 生成相位同步模式的相位同步模式生成部45，用于基于发送/接收时钟来调整主机终端结合的用于从可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将生成的相位同步模式发送到主机终端，并且其中相位同步模式包括持续至少两个周期的第一电平信号，以及跟随第一电平信号并持续的第二电平信号 提供一个循环。

公开(公告)号：US20090052600A1

公开(公告)日：2009-02-26

申请号：US11841922

申请日：2007-08-20

申请人： YUNG-TAI CHEN ,  HSIN-HSIEN LI

发明人： YUNG-TAI CHEN ,  HSIN-HSIEN LI

IPC分类号： H04L27/10

CPC分类号： H04L25/14 ,  H04L7/033 ,  H04L7/046 ,  H04L7/06 ,  H04L25/0272

摘要： A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received data and provide a third signal indicating whether a phase in-lock status is reached, and a detector configured to generate the first signal based on the second signal and the third signal.

摘要翻译： 一种数据通信系统，包括：第一发射机组，被配置为基于第一信号发射第一输出，所述第一输出包括训练模式和第一数据之一，所述训练模式和所述第一数据包括时钟信息;第二发射机组 被配置为基于所述第一信号发送第二输出，所述第二输出包括所述训练模式和第二数据之一;被配置为基于所述第一输出生成第一接收数据的第一接收机组，被配置为生成 基于第二输出的第二接收数据，被配置为基于第一信号和第一接收数据提取时钟信息的时钟和数据恢复（CDR）电路，并提供指示是否达到频率锁定状态的第二信号 ，所述第二接收机组中的相位控制电路，所述相位控制电路被配置为检测所述第一接收数据之间的相位差 和第二接收数据，并提供指示是否达到相位锁定状态的第三信号，以及被配置为基于第二信号和第三信号产生第一信号的检测器。