公开(公告)号：US11853766B2

公开(公告)日：2023-12-26

申请号：US17872927

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Vy Vo ,  Dipanjan Sengupta ,  Mariano Tepper ,  Javier Sebastian Turek

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/50 ,  G06F12/0815 ,  G06N3/063 ,  G06F11/34 ,  G06F18/21 ,  G06N3/045

CPC classification number: G06F9/3877 ,  G06F9/321 ,  G06F9/5016 ,  G06F9/5066 ,  G06F11/3457 ,  G06F12/0815 ,  G06F18/217 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1021

Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.

公开(公告)号：US11853757B2

公开(公告)日：2023-12-26

申请号：US16811011

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Ilya Burylov ,  Mikhail Plotnikov ,  Hideki Ido ,  Ruslan Arutyunyan

IPC: G06F8/41 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30036 ,  G06F8/4441 ,  G06F8/4452 ,  G06F9/30018 ,  G06F9/30065 ,  G06F9/321

Abstract: Systems, apparatuses and methods may provide for technology that identifies that an iterative loop includes a first code portion that executes in response to a condition being satisfied, generates a first vector mask that is to represent one or more instances of the condition being satisfied for one or more values of a first vector of values, and one or more instances of the condition being unsatisfied for the first vector of values, where the first vector of values is to correspond to one or more first iterations of the iterative loop, and conducts a vectorization process of the iterative loop based on the first vector mask.

公开(公告)号：US11803385B2

公开(公告)日：2023-10-31

申请号：US17548105

申请日：2021-12-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh Lagudu ,  Arun Vaidyanathan Ananthanarayan ,  Michael Mantor ,  Allen H. Rush

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/80 ,  G06F9/38 ,  G06T1/20

CPC classification number: G06F9/321 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/80 ,  G06T1/20

Abstract: An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.

公开(公告)号：US11782717B2

公开(公告)日：2023-10-10

申请号：US17819605

申请日：2022-08-12

Applicant: Seagate Technology LLC

Inventor： Marc Tim Jones

IPC: G06F9/30 ,  G06F9/32 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F9/4837 ,  G06F13/4221 ,  G06F2213/0026

Abstract: The technology disclosed herein pertains to a system and method for profiling performance of an embedded computation instruction set (CIS), the method including receiving a profiling component to a computational storage device (CSD), the profiling component being configured to measure one or more execution parameters of a computational instruction set (CIS), executing the CIS at a program slot in a computational storage processor of the CSD, monitoring the execution of the CIS to generate a log of the execution parameters of the CIS, and communicating the log to a host in response to receiving a get-log page command.

公开(公告)号：US11775360B2

公开(公告)日：2023-10-03

申请号：US17671619

申请日：2022-02-15

Applicant: NEC Laboratories Europe GmbH

Inventor： Samira Briongos ,  Claudio Soriente

IPC: G06F9/54 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F9/546 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/321 ,  G06F9/542

Abstract: A method executes inter-enclave communication via cache memory of a processor. The method includes: instantiating a first enclave such that it is configured to execute a first communication thread, which is configured to read/write data to the cache memory; instantiating a second enclave such that it is configured to execute a second communication thread, which is configured to read/write data to cache memory; executing, by the first enclave, the first communication thread to send message data to the second enclave, executing the first communication thread comprising writing the message data to the cache memory; and executing, by the second enclave, the second communication thread to receive the message data. Executing the second communication thread can include: monitoring the cache memory to determine whether the data message is being sent; and based upon determining the data message is being sent, reading from the cache memory to receive the data message.

公开(公告)号：US11755473B2

公开(公告)日：2023-09-12

申请号：US17848716

申请日：2022-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Surendra Singh ,  Dinesh Gehlot ,  Mallikarjun Shivappa Bidari ,  Raju Udava Siddappa ,  Shashank Vimal ,  Shreya Ganatra ,  Sujay Shankar Gaitonde ,  Tushar Vrind ,  Venkata Raju Indukuri

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F12/0253 ,  G06F9/3004 ,  G06F9/321 ,  G06F12/0238

Abstract: A method for managing memory leaks in a memory device includes grouping, by a garbage collection system, a plurality of similar memory allocations of the memory device into one or more Unique Fixed Identifiers (UFIs); identifying, by the garbage collection system, one of the one or more UFIs having a highest accumulated memory size and adding each of the plurality of memory allocations in the identified one of the one or more UFIs into a Potential Leak Candidate List (PLCL); identifying, by the garbage collection system, the memory leaks in the memory device by identifying unreferenced memory addresses associated with the plurality of memory allocations in the PLCL; and releasing, by the garbage collection system, the identified unreferenced memory addresses associated with the plurality of memory allocations corresponding to the memory leaks into the memory device.

公开(公告)号：US11755327B2

公开(公告)日：2023-09-12

申请号：US16806342

申请日：2020-03-02

Applicant: Microsoft Technology Licensing, LLC

Inventor： Melinda Joyce Brown ,  Michael Scott Mcilvaine

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/321 ,  G06F9/30054 ,  G06F9/381 ,  G06F9/3867 ,  G06F9/544

Abstract: Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices is disclosed. In this regard, a processing element (PE) of a processor-based device provides an execution pipeline circuit that comprises an instruction processing portion and a data access portion. Using a literal data access logic circuit, the PE detects a PC-relative load instruction within a fetch window that includes multiple fetched instructions. The PE determines that the PC-relative load instruction can be serviced using literal data that is available to the instruction processing portion of the execution pipeline circuit (e.g., located within the fetch window containing the PC-relative load instruction, or stored in a literal pool buffer), The PE then retrieves the literal data within the instruction processing portion of the execution pipeline circuit, and executes the PC-relative load instruction using the literal data.

公开(公告)号：US11714650B2

公开(公告)日：2023-08-01

申请号：US17709486

申请日：2022-03-31

Applicant: FUJITSU LIMITED

Inventor： Hiroki Tokura ,  Masato Nakagawa ,  Tomotake Nakamura

IPC: G06F9/30 ,  G06F9/32 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/30152 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/324 ,  G06F11/3471 ,  G06F11/3604

Abstract: The present disclosure relates to a non-transitory computer-readable recording medium storing an analysis program that causes a computer to execute a process. The process includes sampling an instruction address of one of instructions included in a program during execution of the program, identifying a first function that includes the sampled instruction address in an address range, rewriting mark information associated with the identified first function, identifying first information corresponding to the instruction address of the first function among a plurality of first information based on the rewritten mark information, identifying second information corresponding to the instruction address of the first function among a plurality of second information based on the rewritten mark information, storing the first information and the second information in a memory, and analyzing performance of the program based on the first information and the second information stored in the memory.

公开(公告)号：US11698812B2

公开(公告)日：2023-07-11

申请号：US16554940

申请日：2019-08-29

Applicant: Intel Corporation

Inventor： Praveen Kumar Gupta ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Stephen H. Gunther

IPC: G06F9/48 ,  G06F9/32 ,  G06F1/10 ,  G06F1/08 ,  G06F1/3296 ,  G06F1/324

CPC classification number: G06F9/4893 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

公开(公告)号：US11687366B2

公开(公告)日：2023-06-27

申请号：US17260580

申请日：2019-02-18

Applicant: Mitsubishi Electric Corporation

Inventor： Nikam Tanajirao Vijay ,  Patwardhan Kunal

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3009 ,  G06F9/321 ,  G06F9/4818 ,  G06F9/485 ,  G06F9/4812 ,  G06F9/545

Abstract: The present invention provides an interrupt handling system for handling interrupts in a computer system is provided. The interrupt handling system captures and processes the interrupts in a user space of the computer system. The present invention also provides for an interrupt registration method that facilitates interrupt handling in the user space during porting of user applications from one platform to another.