公开(公告)号：US5748548A

公开(公告)日：1998-05-05

申请号：US711132

申请日：1996-09-09

Applicant: Silvia Padoan ,  Marco Olivo ,  Carla Golla

Inventor： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC classification number: G11C5/143 ,  G11C16/30 ,  G11C5/147

Abstract: A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

公开(公告)号：US5748029A

公开(公告)日：1998-05-05

申请号：US624126

申请日：1996-03-29

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H01L21/8234 ,  H01L27/088 ,  H03K17/16 ,  H03K17/687

CPC classification number: H03K17/6874 ,  H03K17/162 ,  H03K2217/0018

Abstract: A switching circuit utilizing MOS transistors without body effect having a first transistor inserted with source and drain terminals between two connection terminals, and a second and third transistors inserted in series by means of their respective source and drain terminals between the first transistor and a ground. The gate terminal of the second transistor is connected to the gate terminal of the first transistor to which is applied a command signal. Upon switching a signal is applied in phase opposition to the command signal to the gate terminal of the third transistor. The substrates of the first and the second transistors are connected to a connection node between the second and third transistors. The substrate of the third transistor is connected to ground.

Abstract translation: 利用具有体效应的MOS晶体管的开关电路具有在两个连接端子之间插入源极和漏极端子的第一晶体管，以及通过其第一晶体管和地之间的各自的源极和漏极端子串联插入的第二和第三晶体管。 第二晶体管的栅极端子连接到施加有命令信号的第一晶体管的栅极端子。 在切换时，与第三晶体管的栅极端子相反地施加与指令信号相反的信号。 第一和第二晶体管的基板连接到第二和第三晶体管之间的连接节点。 第三晶体管的基板连接到地。

公开(公告)号：US5747978A

公开(公告)日：1998-05-05

申请号：US622459

申请日：1996-03-22

Applicant: Roberto Gariboldi ,  Francesco Pulvirenti

Inventor： Roberto Gariboldi ,  Francesco Pulvirenti

IPC: G01R19/165 ,  G05F1/46 ,  G05F3/26 ,  G05F3/28 ,  G05F3/30 ,  G11C5/14 ,  H02J1/00 ,  G05F3/16

CPC classification number: G11C5/147 ,  G05F1/465 ,  G05F3/267

Abstract: A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator having an input terminal and an output terminal, and a voltage divider connected between a first supply voltage reference and a second voltage reference and connected to the input terminal of the comparator, further provides for the output terminal of said comparator to be connected to the input terminal through at least one feedback network comprising at least one current generator. The feedback network further comprises a buffer block having an input terminal connected to said comparator and a first output terminal connected to a switch which is connected between a circuit node of said voltage divider and the second voltage reference.

Abstract translation: 一种用于产生参考电压并检测电源电压下降的电路，包括至少一个具有输入端和输出端的阈值比较器，以及分压器，连接在第一电源电压基准和第二电压基准之间，并连接到 比较器的输入端还通过包括至少一个电流发生器的至少一个反馈网络提供所述比较器的输出端子连接到输入端子。 反馈网络还包括缓冲块，其具有连接到所述比较器的输入端子和连接到开关的第一输出端子，该开关连接在所述分压器的电路节点和第二参考电压之间。

公开(公告)号：US5737268A

公开(公告)日：1998-04-07

申请号：US684431

申请日：1996-07-19

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C11/4091 ,  G11C7/00

CPC classification number: G11C11/4091

Abstract: A latch arrangement, having a load, receives an equalization signal to control the timing of data sensing and data capture. The slope of the equalization signal is modulated so that it has two slopes: a less steep one which permits evaluation of a datum with appropriate caution, and a much steeper slope, which occurs at the end of reliable evaluation, to capture the datum and store it. The equalization signal is generated by first presetting the equalization signal to a first value. Thereafter a change in the equalization signal from the first value to a second value is initiated. After initiating the change in the equalization signal, the equalization signal is slowly discharged at a first slope. A ratio between a current generated in a generic matrix cell applied to the load of the latch arrangement and a reference current is evaluated. When the evaluated ratio reaches a desired level, the equalization signal is quickly discharged to the second value at a second slope.

Abstract translation: 具有负载的锁存装置接收均衡信号以控制数据检测和数据捕获的定时。 调整均衡信号的斜率，使其具有两个斜率：较不陡的斜率，允许在适当谨慎的情况下对基准进行评估，并且在可靠评估结束时出现更陡峭的斜率，以捕获基准和存储 它。 通过首先将均衡信号预设为第一值来产生均衡信号。 此后，启动从第一值到第二值的均衡信号的改变。 在启动均衡信号的变化之后，均衡信号以第一斜率缓慢放电。 评估在施加到锁存装置的负载的一般矩阵单元中产生的电流与参考电流之间的比率。 当评估比达到期望水平时，均衡信号以第二斜率快速地排放到第二值。

公开(公告)号：US5735254A

公开(公告)日：1998-04-07

申请号：US639794

申请日：1996-04-29

Applicant: Sergio Palara ,  Stefano Sueri ,  Salvatore Scaccianoce

Inventor： Sergio Palara ,  Stefano Sueri ,  Salvatore Scaccianoce

IPC: G01R19/165 ,  F02P17/12 ,  G01R29/027 ,  H01T13/60 ,  H02H3/08 ,  H02H3/20

CPC classification number: H01T13/60 ,  F02P17/12 ,  G01R29/0273

Abstract: A circuit for use with an ignition system to enable detection of an overvoltage condition in the primary winding of an ignition coil caused by opening of a power switch connected to the primary winding. The circuit senses the overvoltage condition by comparing the voltage on the primary winding to a first threshold voltage and produces a signal at an output terminal indicative of the presence of the overvoltage condition. The output terminal is maintained at a high logic level upon detection of an overvoltage condition and throughout the time duration of the overvoltage condition, and drops to a low logic level when the voltage on the primary winding falls to a second threshold voltage, which is lower than the first threshold voltage. Comparison circuitry is provided for sensing the overvoltage condition by reference to fixed voltage values. Logic circuitry responds to the comparison circuitry to produce the appropriate logic levels at the output terminal.

Abstract translation: 一种与点火系统一起使用的电路，用于检测由连接到初级绕组的电源开关的断开引起的点火线圈的初级绕组中的过电压状态。 电路通过将初级绕组上的电压与第一阈值电压进行比较来感测过电压状态，并在输出端产生指示存在过电压状态的信号。 在检测到过电压状态并且在过电压状态的整个持续时间期间，输出端子保持在高逻辑电平，并且当初级绕组上的电压下降到第二阈值电压时下降到低逻辑电平，这是较低的 比第一阈值电压。 提供比较电路用于通过参考固定电压值来感测过电压状态。 逻辑电路响应于比较电路，以在输出端产生适当的逻辑电平。

公开(公告)号：US5731696A

公开(公告)日：1998-03-24

申请号：US537340

申请日：1995-07-24

Applicant: Alessio Pennisi ,  Fabio Marchio ,  Jean Marie Pierret ,  Francois Brandy

Inventor： Alessio Pennisi ,  Fabio Marchio ,  Jean Marie Pierret ,  Francois Brandy

IPC: G05F1/46 ,  G05F3/22 ,  G05F3/30 ,  G05F3/16

CPC classification number: G05F3/225 ,  G05F1/463 ,  G05F3/30

Abstract: A voltage reference circuit with programmable thermal coefficient, comprising first and second bipolar transistors having their base terminals connected together and collector terminals connected to two legs of a current mirror circuit. The emitter terminal of the first transistor is connected to ground through two resistors in series with each other, and the emitter terminal of the second transistor is connected to a node between the two resistors. The emitter of at least one of the two transistors has discrete portions adapted to be connected electrically together in a predetermined fashion.

Abstract translation: 具有可编程热系数的电压参考电路，包括其基极端子连接在一起的第一和第二双极晶体管，以及连接到电流镜电路的两个支路的集电极端子。 第一晶体管的发射极端子通过彼此串联的两个电阻器连接到地，并且第二晶体管的发射极端子连接到两个电阻器之间的节点。 两个晶体管中的至少一个晶体管的发射极具有适于以预定方式电连接的分立部分。

公开(公告)号：USRE35745E

公开(公告)日：1998-03-17

申请号：US395135

申请日：1995-02-27

Applicant: Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

Inventor： Andrea Barsanti ,  Claudio Diazzi ,  Fabio Vio

IPC: H03K17/06 ,  H03K17/10

CPC classification number: H03K17/063

Abstract: This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block, a capacitive bootstrap circuit and a reference voltage generating block generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.

公开(公告)号：US5723350A

公开(公告)日：1998-03-03

申请号：US70084

申请日：1993-05-28

Applicant: Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

Inventor： Gabriella Fontana ,  Orio Bellezza ,  Giuseppe Paolo Crisenza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An improved fabrication process employing relatively non-critical masks permits the fabrication of high density electrically programmable and erasable EEPROM or FLASH-EPROM devices. In practice the novel process permits the fabrication of a contactless, cross-point array providing for a more comfortable "pitch" of bitline metal-definition while realizing a cell layout with a gate structure which extends laterally over adjacent portions of field oxide, thus establishing an appropriate capacitive coupling between control and floating gates. Two alternative embodiments are described.

公开(公告)号：US5708604A

公开(公告)日：1998-01-13

申请号：US789616

申请日：1997-01-27

Applicant: Marco Fontana ,  Luigi Pascucci

Inventor： Marco Fontana ,  Luigi Pascucci

IPC: G11C8/08 ,  G11C16/06

CPC classification number: G11C8/08

Abstract: A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.

Abstract translation: 用于在较低电源电压下工作的电池供电设备的EPROM，EEPROM或FLASH EPROM的最终解码级的驱动电路通过切换p沟道下拉单元的控制节点的电容来避免来自共同升压的电压节点的能量吸收， 该CMOS反相器驱动存储器线并构成驱动电路的负载。 该节点通过从电源节点引出电流被有效地充电，并且通过并联地切换预先放电的电容而迅速放电。 该电荷共享可切换电容可以有利地是阵列的未选择的字线的类似的p沟道上拉控制节点的电容。

公开(公告)号：US5684425A

公开(公告)日：1997-11-04

申请号：US394671

申请日：1995-02-27

Applicant: Germano Nicollini ,  Pierangelo Confalonieri

Inventor： Germano Nicollini ,  Pierangelo Confalonieri

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/6872 ,  H03K17/162

Abstract: Electronic switch for low-voltage supply circuits completed with CMOS technology and comprising a first, a second and a third circuit element (SW1 ,SW2,SW3) consisting each of a pair of complementary transistors. The first and second of said elements (SW1,SW2) are inserted between two connection terminals of the switch (A,B) while the third element SW3 is inserted between a node (C) included between the first and the second element of a voltage reference (VCM). The first and second element are driven to conduction in phases (.phi.1) not overlapping the phases (.phi.2) in which it conducts the third element.

Abstract translation: 用CMOS技术完成的低电压电路的电子开关，包括由一对互补晶体管组成的第一，第二和第三电路元件（SW1，SW2，SW3）。 所述元件（SW1，SW2）中的第一和第二元件插入在开关（A，B）的两个连接端子之间，而第三元件SW3插入在包含在电压的第一和第二元件之间的节点 参考（VCM）。 第一和第二元件被驱动以不与其传导第三元件的相（phi 2）重叠的相（phi 1）传导。