公开(公告)号：US20220171635A1

公开(公告)日：2022-06-02

申请号：US17673647

申请日：2022-02-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Steven Tony Tye ,  Brian Laird Sumner ,  Konstantin Zhuravlyov

IPC: G06F9/445 ,  G06F8/76

Abstract: Described herein are techniques for executing a heterogeneous code object executable. According to the techniques, a loader identifies a first memory appropriate for loading a first architecture-specific portion of the heterogeneous code object executable, wherein the first architecture specific portion includes instructions for a first architecture, identifies a second memory appropriate for loading a second architecture-specific portion of the heterogeneous code object executable, wherein the second architecture specific portion includes instructions for a second architecture that is different than the first architecture, loads the first architecture-specific portion into the first memory and the second architecture-specific portion into the second memory, and performs relocations on the first architecture-specific portion and on the second architecture-specific portion.

公开(公告)号：US11347925B2

公开(公告)日：2022-05-31

申请号：US15636278

申请日：2017-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G06F30/394 ,  G06F30/39 ,  G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  H01L27/118

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.

公开(公告)号：US20220147668A1

公开(公告)日：2022-05-12

申请号：US17094690

申请日：2020-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Nicholas Malaya ,  Jakub Kurzak

IPC: G06F30/27 ,  G06F17/18 ,  G06K9/62

Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.

公开(公告)号：US11321241B2

公开(公告)日：2022-05-03

申请号：US17008435

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  Michael W. LeBeane

IPC: G06F12/1027 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/0846

Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.

公开(公告)号：US20220130342A1

公开(公告)日：2022-04-28

申请号：US17134770

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： ASHISH JAIN ,  DHIRENDRA PARTAP SINGH RANA ,  SAMUEL NAFFZIGER ,  GIA TUNG PHAN ,  BENJAMIN TSIEN

IPC: G09G3/36 ,  G09G3/20 ,  G06F12/0895 ,  G06F12/0811 ,  G06F1/3234

Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

公开(公告)号：US20220129752A1

公开(公告)日：2022-04-28

申请号：US17571045

申请日：2022-01-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sateesh Lagudu ,  Lei Zhang ,  Allen Rush

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for implementing memory bandwidth reduction techniques for low power convolutional neural network inference applications are disclosed. A system includes at least a processing unit and an external memory coupled to the processing unit. The system detects a request to perform a convolution operation on input data from a plurality of channels. Responsive to detecting the request, the system partitions the input data from the plurality of channels into 3D blocks so as to minimize the external memory bandwidth utilization for the convolution operation being performed. Next, the system loads a selected 3D block from external memory into internal memory and then generates convolution output data for the selected 3D block for one or more features. Then, for each feature, the system adds convolution output data together across channels prior to writing the convolution output data to the external memory.

公开(公告)号：US11315883B2

公开(公告)日：2022-04-26

申请号：US16680978

申请日：2019-11-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC: H01L23/544 ,  H01L23/18 ,  H01L23/12

Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US20220122652A1

公开(公告)日：2022-04-21

申请号：US17564575

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：US11301410B1

公开(公告)日：2022-04-12

申请号：US17120208

申请日：2020-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Gordon Caruk

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/40 ,  G06F15/173 ,  G06F13/364

Abstract: An electronic device includes a requester and a link interface coupled between the requester and a link. The requester is configured to send a request packet to a completer on the link via the link interface. When sending the request packet to the completer, the requester sends, to the completer via the link interface, the request packet with a tag that is not unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer before the request packet is in the internal elements of the completer, but that is unique with respect to tags in other request packets from the requester that will be in the internal elements of the completer while the request packet is in the internal elements of the completer.

公开(公告)号：US11295507B2

公开(公告)日：2022-04-05

申请号：US17091957

申请日：2020-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Leather ,  Michael Mantor

IPC: G06T15/00 ,  G06F9/48 ,  G06T1/20

Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.