Memory Access Tracking Using a Peripheral Device

    公开(公告)号:US20230133439A1

    公开(公告)日:2023-05-04

    申请号:US17536141

    申请日:2021-11-29

    Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

    Template-Based Packet Parsing
    423.
    发明申请

    公开(公告)号:US20230127568A1

    公开(公告)日:2023-04-27

    申请号:US17508998

    申请日:2021-10-24

    Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with. the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

    Synthesized clock synchronization between network devices

    公开(公告)号:US11637557B2

    公开(公告)日:2023-04-25

    申请号:US17670540

    申请日:2022-02-14

    Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.

    Pacing in a storage sub-system
    429.
    发明授权

    公开(公告)号:US11609700B2

    公开(公告)日:2023-03-21

    申请号:US17505670

    申请日:2021-10-20

    Abstract: One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

    Chip security verification tool
    430.
    发明授权

    公开(公告)号:US11599703B2

    公开(公告)日:2023-03-07

    申请号:US16783237

    申请日:2020-02-06

    Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.

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