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公开(公告)号:US20230133439A1
公开(公告)日:2023-05-04
申请号:US17536141
申请日:2021-11-29
Applicant: Mellanox Technologies, Ltd.
Inventor: Ran Avraham Koren , Ariel Shahar , Liran Liss , Gabi Liron , Aviad Shaul Yehezkel
IPC: G06F12/0882 , G06F12/0831 , G06F13/16
Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.
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公开(公告)号:US20230132571A1
公开(公告)日:2023-05-04
申请号:US17520093
申请日:2021-11-05
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Paraskevas Bakopoulos , Ioannis (Giannis) Patronas , Dimitris Syrivelis , Liron Mula , Aviad Levy , Elad Mentovich
Abstract: Devices, networking devices, and switches, among other things, are disclosed. An illustrative switch is disclosed to include a plurality of optical Input/Output (I/O) ports; a multi-chip module (MCM) assembly including switching circuitry and at least one chiplet that is optically coupled with one of the plurality of optical I/O ports; and a controller coupled with the at least one chiplet and configured to couple the at least one chiplet with a Quantum Key Distribution (QKD) device.
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公开(公告)号:US20230127568A1
公开(公告)日:2023-04-27
申请号:US17508998
申请日:2021-10-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Gil Levy , Liron Mula , Barak Gafni
Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with. the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.
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公开(公告)号:US11637557B2
公开(公告)日:2023-04-25
申请号:US17670540
申请日:2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号:US20230120745A1
公开(公告)日:2023-04-20
申请号:US17503383
申请日:2021-10-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Niv Aibester , Gil Levy , Liron Mula , Barak Gafni , Aviv Kfir
IPC: H04L12/861 , H04L12/879 , H04L12/933 , H04L12/925 , H04L12/911
Abstract: A network device includes multiple ports, packet processing circuitry, a memory and a reserved-memory management circuit (RMMC). The ports are to communicate packets over a network. The packet processing circuitry is to process the packets using a plurality of queues. The memory is to store a shared buffer. The RMMC is to allocate segments of the shared buffer to the queues, including allocating reserve segments of the shared buffer to selected queues that meet a reserve-allocation criterion.
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公开(公告)号:US20230110285A1
公开(公告)日:2023-04-13
申请号:US17500598
申请日:2021-10-13
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Ilan Pardo , Benjamin Fuhrer , Noam Korem , Gal Yefet , Tomer Bar-On
IPC: G06N3/04
Abstract: Apparatuses, systems, and techniques to improve processing efficiency are provided. In at least one embodiment, a processing unit is described as including circuitry that receives an input vector and applies an activation function to the input vector by performing a hardware approximation of the activation function in a vector manner. The circuitry also generates an output vector based on the activation function.
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公开(公告)号:US11627684B2
公开(公告)日:2023-04-11
申请号:US16810248
申请日:2020-03-05
Applicant: Mellanox Technologies, Ltd.
Inventor: Ayal Shabtay , Shay Zaretsky , Yogev Buzaglo
Abstract: A bi-directional fan device that is field replaceable within an electronic system is provided. The bi-directional fan device includes a fan unit that cools an electronic system when connected to a power source, and an electrical connector constructed at both ends of the fan unit to electrically connect to the power source.
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公开(公告)号:US11616315B2
公开(公告)日:2023-03-28
申请号:US17308807
申请日:2021-05-05
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Jamal Mousa , Nimer Khazen , Uri Goffer-Dor , Dmitry Fliter , David Fischer , Alona Najmanovich , Tarek Hathoot , Dor Dadon
IPC: H01R12/75 , H01R12/72 , H01R24/64 , H01R107/00
Abstract: A connector for a networking cable assembly includes a substrate, a first set of contacts on a first surface of the substrate that electrically connect to leads of a first cable, and a second set of contacts on the first surface of the substrate that electrically connect to leads of a second cable. The first set of contacts are spaced apart from the second set of contacts in a first direction by an amount that enables the second cable to be stacked on the first cable and passed over the first set of contacts to electrically connect to the leads of the second cable.
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公开(公告)号:US11609700B2
公开(公告)日:2023-03-21
申请号:US17505670
申请日:2021-10-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Shridhar Rasal , Laxman Kumar Dewangan , Oren Duer , Eliav Bar-Ilan , Leslin Varghese , Prateek Patel , Karem Kobti , Krishna Kishore Yarlagadda
Abstract: One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.
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公开(公告)号:US11599703B2
公开(公告)日:2023-03-07
申请号:US16783237
申请日:2020-02-06
Applicant: Mellanox Technologies, Ltd.
Inventor: Dotan Finkelstein , Roman Manevich , Lidiya Ivanitskaya
IPC: G06F30/398 , G06F21/72 , G06F119/02
Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.
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