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    TIME DOMAIN MULTIPLY AND ACCUMULATE SYSTEM
    431.
    发明申请
    TIME DOMAIN MULTIPLY AND ACCUMULATE SYSTEM 有权

    公开(公告)号：US20220091822A1

    公开(公告)日：2022-03-24

    申请号：US17028723

    申请日：2020-09-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ravinder Reddy Rachala ,  Stephen Victor Kosonocky ,  Miguel Rodriguez

    IPC: G06F7/544 ,  H03K21/08

    Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

    Power management advisor to support power management control
    435.
    发明授权
    Power management advisor to support power management control 有权

    公开(公告)号：US11275430B2

    公开(公告)日：2022-03-15

    申请号：US16115420

    申请日：2018-08-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Greg Sadowski ,  Ying Chen

    IPC: G06F1/32 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/3287

    Abstract: An apparatus includes a plurality of registers to store sets of state information that represent a state history of a processing unit. The apparatus also includes a power management advisor (PMA) to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller including hardware circuitry that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.

    ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT
    436.
    发明申请
    ALTERNATE PATH FOR BRANCH PREDICTION REDIRECT 有权

    公开(公告)号：US20220075624A1

    公开(公告)日：2022-03-10

    申请号：US17012833

    申请日：2020-09-04

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Ashok T. VENKATACHAR ,  Robert COHEN ,  Steven R. HAVLIR ,  Aparna Chandrashekhar MANDKE ,  Tzu-Wei LIN ,  Bhawna NAYAK

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F12/1027

    Abstract: Branch prediction circuitry predicts an outcome of a branch instruction. A pipeline circuitry processes instructions along a first path from a predicted branch of the branch instruction. The instructions along the first path are processed concurrently with processing instructions along a second path from an unpredicted branch of the branch instruction. Information representing the state of the second portion while processing the second path is stored in one or more buffers. The instructions are processed along the second path using the information stored in the buffers in response to a misprediction of the outcome of the branch instruction. In some cases, the branch prediction circuitry determines a confidence level for the predicted outcome and the instructions along the second path from the unpredicted branch are processed in response to the confidence level being below a threshold confidence.

    SHADER CORE INSTRUCTION TO INVOKE DEPTH CULLING
    437.
    发明申请
    SHADER CORE INSTRUCTION TO INVOKE DEPTH CULLING 有权

    公开(公告)号：US20220068012A1

    公开(公告)日：2022-03-03

    申请号：US17007935

    申请日：2020-08-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Matthäus G. Chajdas ,  Christopher J. Brennan

    IPC: G06T15/40 ,  G06F9/30 ,  G06T15/00

    Abstract: Systems, apparatuses, and methods for executing a shader core instruction to invoke depth culling are disclosed. A shader core executes an instruction to invoke a culling function on a depth culling unit for one or more entities prior to completing a corresponding draw call. The shader core provides a mode and coordinates to the depth culling unit as a result of executing the instruction. The depth culling unit implements the culling function to access a live depth buffer to determine whether one or more primitives corresponding to the entities are occluded. The culling unit returns indication(s) to the shader core regarding the result(s) of processing the one or more primitives. For example, if the results indicate a primitive is occluded, the shader core cancels the draw call for the primitive.

    INDIRECT CHAINING OF COMMAND BUFFERS
    440.
    发明申请
    INDIRECT CHAINING OF COMMAND BUFFERS 有权

    公开(公告)号：US20220058767A1

    公开(公告)日：2022-02-24

    申请号：US17519992

    申请日：2021-11-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Hans Fernlund ,  Mitchell H. Singer ,  Manu Rastogi

    IPC: G06T1/20 ,  G06F9/30 ,  G09G5/395 ,  G09G5/36 ,  G06T1/60

    Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

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