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公开(公告)号:US10247881B2
公开(公告)日:2019-04-02
申请号:US15491718
申请日:2017-04-19
Applicant: STMicroelectronics, Inc.
Inventor: John H. Zhang
IPC: H01L21/4763 , G02B6/132 , G02B6/122 , H01L23/522 , G02B6/13 , H01L21/768 , G02B6/136 , H01L23/532 , H01L21/66 , G02B6/12
Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
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公开(公告)号:US10242862B2
公开(公告)日:2019-03-26
申请号:US15391135
申请日:2016-12-27
Applicant: STMicroelectronics, Inc.
Inventor: John H. Zhang
Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing—rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.
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433.
公开(公告)号:US20190081079A1
公开(公告)日:2019-03-14
申请号:US16180223
申请日:2018-11-05
Applicant: STMicroelectronics, Inc.
Inventor: Qing Liu , Pierre Morin
IPC: H01L27/12 , H01L27/092 , H01L29/66 , H01L21/02 , H01L21/324 , H01L21/3105 , H01L21/308 , H01L21/8238 , H01L29/78 , H01L21/84 , H01L29/06 , H01L29/10
Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).
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公开(公告)号:US20190068193A1
公开(公告)日:2019-02-28
申请号:US16142627
申请日:2018-09-26
Applicant: STMicroelectronics, Inc.
Inventor: Chetan BISHT , Harry SCRIVENER
IPC: H03K19/0175 , G06F17/50 , H01L23/528 , H01L23/50
Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.
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435.
公开(公告)号:US20190047289A1
公开(公告)日:2019-02-14
申请号:US16165484
申请日:2018-10-19
Applicant: STMicroelectronics, Inc.
Inventor: Murray J. Robinson , Kenneth J. Stewart
Abstract: A method of making inkjet print heads may include forming recesses in a first surface of a first wafer to define inkjet chambers. The method may also include forming openings extending from a second surface of the first wafer through to respective ones of the inkjet chambers to define inkjet orifices. The method may further include forming a second wafer including ink heaters, and joining the first and second wafers together so that the ink heaters are aligned within respective inkjet chambers to thereby define the inkjet print heads.
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公开(公告)号:US20190043790A1
公开(公告)日:2019-02-07
申请号:US16154538
申请日:2018-10-08
Applicant: STMicroelectronics, Inc.
Inventor: Rennier Rodriguez , Aiza Marie Agudon , Jefferson Talledo , Moonlord Manalo , Ela Mia Cadag , Rammil Seguido
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31
Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
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公开(公告)号:US20190028853A1
公开(公告)日:2019-01-24
申请号:US16137980
申请日:2018-09-21
Applicant: STMicroelectronics, Inc.
Inventor: Oleg Logvinov , Aidan Cully , David Lawrence , Michael Macaluso
IPC: H04W4/06 , H04L29/06 , H04L1/18 , H04L12/18 , H04W74/08 , H04L12/413 , H04B3/54 , H04L12/761 , H04L1/00
Abstract: Multicast transmissions do not allow for individual receivers to acknowledge that data was received by each receiver in the network. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol supports using multicast transmissions (one-to-many) in multimedia isochronous systems. A transmitter establishes a Multi-ACKed Multicast protocol within which a group of receiving devices can acknowledge the multicast transmission during a multi-acknowledgment period.
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公开(公告)号:US20190006266A1
公开(公告)日:2019-01-03
申请号:US15636533
申请日:2017-06-28
Applicant: STMICROELECTRONICS, INC.
Inventor: Frederick Ray GOMEZ , Tito MANGAOANG, JR. , Jefferson TALLEDO
IPC: H01L23/495 , H01L23/31 , H01L23/00 , H01L21/66 , H01L21/56
CPC classification number: H01L23/4952 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L22/12 , H01L23/3107 , H01L23/49548 , H01L23/60 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2223/544 , H01L2224/04042 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49052 , H01L2224/73265 , H01L2224/83855 , H01L2224/85013 , H01L2224/85424 , H01L2224/85447 , H01L2224/92247 , H01L2224/97 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
Abstract: According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
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公开(公告)号:US10163684B2
公开(公告)日:2018-12-25
申请号:US15831761
申请日:2017-12-05
Inventor: Bruce Doris , Hong He , Qing Liu
IPC: H01L21/762 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/165 , H01L21/02 , H01L21/225 , H01L27/12 , H01L29/66 , H01L29/10 , H01L27/088 , H01L21/8234
Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.
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公开(公告)号:US20180356525A1
公开(公告)日:2018-12-13
申请号:US15617875
申请日:2017-06-08
Applicant: STMicroelectronics, Inc.
Inventor: Dominique Paul Barbier , Xiaoyong Yang
CPC classification number: G01S17/89 , G01S7/4817 , G01S17/10
Abstract: The present disclosure is directed to a method and system for scanning an object or environment with a ranging sensor. The method involves rotating a ranging sensor around a rotation reference point and associating the distances measured with the ranging sensor with rotation measurements from a rotation sensor fixed to the ranging sensor. The associated data is used to populate a data plot or data table to be used to generate three-dimensional models.
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