公开(公告)号：US20210391383A1

公开(公告)日：2021-12-16

申请号：US16924169

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

IPC: H01L27/22 ,  H01L43/02 ,  G11C7/18

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

公开(公告)号：US11195994B2

公开(公告)日：2021-12-07

申请号：US16689100

申请日：2019-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Chen-Yi Weng ,  Si-Han Tsai ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

公开(公告)号：US11195905B2

公开(公告)日：2021-12-07

申请号：US16358556

申请日：2019-03-19

Applicant: United Microelectronics Corp.

Inventor： Hsiang-Hua Hsu ,  Liang-An Huang ,  Sheng-Chen Chung ,  Chen-An Kuo ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Kuang-Hsiu Chen ,  Ke-Feng Lin ,  Yan-Huei Li ,  Kai-Ting Hu

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/778

Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

公开(公告)号：US11189691B2

公开(公告)日：2021-11-30

申请号：US16700504

申请日：2019-12-02

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.

公开(公告)号：US20210359131A1

公开(公告)日：2021-11-18

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US11177377B2

公开(公告)日：2021-11-16

申请号：US16726263

申请日：2019-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/34

Abstract: A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

公开(公告)号：US20210351294A1

公开(公告)日：2021-11-11

申请号：US16896233

申请日：2020-06-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Hsin Huang ,  Chen-An Kuo ,  Po-Chun Lai

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. A top of the isolation structure includes a flat surface, and a bottom of the isolation structure includes a curved surface.

公开(公告)号：US11171227B2

公开(公告)日：2021-11-09

申请号：US16659579

申请日：2019-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/76 ,  H01L21/8258 ,  H01L21/8252 ,  H01L29/06

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.

公开(公告)号：US11171091B2

公开(公告)日：2021-11-09

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US20210343523A1

公开(公告)日：2021-11-04

申请号：US17375211

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen-Zhen WANG ,  Jian-Jun ZHANG

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/423

Abstract: A method for forming a semiconductor structure is provided, which comprises the following steps. A gate is formed by a method comprising the following steps. A gate dielectric layer is formed on a substrate. A gate electrode is formed on the gate dielectric layer. A nitride spacer is formed on a sidewall of the gate electrode. A phosphorus containing dielectric layer is formed on the gate. The phosphorus containing dielectric layer has a varied phosphorus dopant density distribution profile. The phosphorus containing dielectric layer comprises a phosphorus dopant density region on an upper surface of the gate and having a triangle-like shape.