公开(公告)号：USRE38891E1

公开(公告)日：2005-11-22

申请号：US09998593

申请日：2001-11-16

Applicant: Eric J. Danstrom

Inventor： Eric J. Danstrom

IPC: G05F1/00 ,  G05F1/44 ,  G06F1/26

Abstract: A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load capable of operating at either of several consumption levels when the load changes its power consumption level . The load transient compensator has a comparator having an output connected to an input of an upper driver and of a lower driver with the output of each of the driver being connected to a gate of a power transistor. When the load is in sleep mode and is about to start being accessed, the upper driver is turned on to turn on its associated transistor to supply additional current to the load, regulated by the comparison circuit. When the load is in the power up mode and it is about to stop being accessed, the lower driver is turned on to turn on its associated transistor to drain current supplied to the load by a supply, regulated by the comparison circuit. This allows a quicker response to the large changes in current required by the load when the load is changing its level of power consumption without greatly increasing the cost of the system containing the load and without compromising the stability of the system.

Abstract translation: 负载瞬态补偿器和操作负载瞬变补偿器的方法，用于减少负载的瞬态响应时间<？delete-start id =“DEL-S-00001”date =“20051122”？>能够在几种消耗 负载改变其功耗水平时的电平<？delete-end id =“DEL-S-00001”？>。 负载瞬态补偿器具有一个比较器，其输出端连接到上驱动器和下驱动器的输入端，其中每个驱动器的输出端连接到功率晶体管的栅极。 当负载处于睡眠模式并即将开始访问时，上位驱动器被接通以打开其相关联的晶体管，以向比较电路调节的负载提供额外的电流。 当负载处于上电模式并且即将停止访问时，下驱动器被接通以打开其相关联的晶体管，以便通过由比较电路调节的电源来供给负载的电流。 <？delete-start id =“DEL-S-00002”date =“20051122”？>这样可以更快速地响应负载在负载变化其功耗水平时所需的电流大幅变化，而不会大大增加 包含负载的系统的成本，而不影响系统的稳定性。<？delete-end id =“DEL-S-00002”？>

公开(公告)号：US06963460B2

公开(公告)日：2005-11-08

申请号：US10295263

申请日：2002-11-14

Applicant: Manish Jain ,  Roberto Alini

Inventor： Manish Jain ,  Roberto Alini

IPC: G11B20/10 ,  G05F1/10 ,  G11B5/02 ,  G11B5/09 ,  G11B19/00

CPC classification number: G11B19/00 ,  G11B19/2063

Abstract: A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

Abstract translation: 电压调节器包括输出节点和第一和第二调节器电路。 当电源电压等于或超过预定阈值时，第一调节器电路在输出节点上产生第一调节电压，并且当电源电压小于预定阈值时，第二调节器电路在输出节点上产生第二调节电压。

公开(公告)号：US06954219B2

公开(公告)日：2005-10-11

申请号：US10021283

申请日：2001-12-12

Applicant: Theodore H. Hermanson

Inventor： Theodore H. Hermanson

IPC: A63F13/00 ,  G06T3/40 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T3/40

Abstract: A method and system of scaling images on a video display is disclosed. A video data stream is processed into video data, which is displayed on a video display at a predetermined aspect ratio. A user manipulable controller, such as a joystick, is operative with a graphics processor unit for scaling images on the video display by obtaining video source values of pixel width and height to be displayed and determining the smallest integer increment on the x/y axis that will maintain the desired aspect ratio using a greatest common denominator to reduce the ratio to the lowest integer.

Abstract translation: 公开了一种在视频显示器上缩放图像的方法和系统。 视频数据流被处理成以预定的宽高比显示在视频显示器上的视频数据。 诸如操纵杆的用户可操纵控制器与图形处理器单元操作，用于通过获得要显示的像素宽度和高度的视频源值来确定视频显示器上的图像，并且确定x / y轴上的最小整数增量， 将使用最大公分数来保持期望的宽高比，以将比率降低到最低的整数。

公开(公告)号：US06951125B2

公开(公告)日：2005-10-04

申请号：US10062595

申请日：2002-01-31

Applicant: Harry Michael Siegel ,  Anthony M. Chiu

Inventor： Harry Michael Siegel ,  Anthony M. Chiu

IPC: H01L21/60 ,  H01L21/52 ,  H01L21/58 ,  H01L23/544 ,  B21D28/04 ,  B23K1/20 ,  G01R31/02 ,  H01L23/48

CPC classification number: H01L21/52 ,  H01L23/544 ,  H01L24/48 ,  H01L24/83 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/854 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits a form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.

Abstract translation: 公开了用于使集成电路基板上的集成电路管芯对准的系统和方法。 将多个可变形材料的沉积物放置在集成电路芯片对准的基板上。 在一个有利的实施例中，冲压工具被转位到第一工具孔和衬底中的第二工具孔。 冲压工具将可变形材料的沉积物相对于第一和第二工具孔印刷到小于百微米的公差。 沉积物的印记部分形成用于接收集成电路管芯的口袋。 这使得集成电路管芯能够在三维尺寸上精确地对准衬底。

公开(公告)号：US06927610B2

公开(公告)日：2005-08-09

申请号：US10912371

申请日：2004-08-05

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03B1/00 ,  H03K3/00 ,  H03K4/502 ,  H03K4/90 ,  H03K5/08 ,  H03K5/12 ,  H03K5/13 ,  H03K17/16

CPC classification number: H03K17/166 ,  H03K4/502 ,  H03K5/08 ,  H03K5/13

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract translation: 用于确保用于从最大电压到最小电源电压（例如地）的功率驱动级的转换速率控制的电容器的高度线性放电的方法和结构。 电压斜坡发生器使用单个级联电流源来实现线性斜坡下降。

公开(公告)号：US20050161784A1

公开(公告)日：2005-07-28

申请号：US11005868

申请日：2004-12-06

Applicant: Anthony Chiu ,  Harry Siegel

Inventor： Anthony Chiu ,  Harry Siegel

IPC: G06K9/00 ,  H01L29/00 ,  H01L23/02 ,  H01L23/495

CPC classification number: G06K9/0002

Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

Abstract translation: 在模具的上模具部分和下模具部分之间容纳平坦的过滤层，用于将由模具保持的集成电路传感器装置封装在集成电路的感测表面上并与集成电路的感测表面接触，以在感测表面和模具表面之间的轻压缩。 过滤层包括允许注入的封装材料通过以覆盖集成电路管芯的槽，其中重叠部分嵌入在封装材料中，同时防止这种封装材料流入感测表面。 过滤层可以是例如液体和/或光过滤器，并且可以包括保护性或支撑性背衬。 因此，过滤器被固定到封装的集成电路传感器装置上，同时减少了模具残渣并延长了模具寿命。

公开(公告)号：US06922773B2

公开(公告)日：2005-07-26

申请号：US09751408

申请日：2000-12-29

Applicant: Paolo Faraboschi ,  Alexander J. Starr ,  Anthony X. Jarvis ,  Geoffrey M. Brown ,  Mark Owen Homewood ,  Gary L. Vondran

Inventor： Paolo Faraboschi ,  Alexander J. Starr ,  Anthony X. Jarvis ,  Geoffrey M. Brown ,  Mark Owen Homewood ,  Gary L. Vondran

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34

CPC classification number: G06F9/3891 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3853 ,  G06F9/3885

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract translation: 为了在包括N个处理级的指令执行流水线的数据处理器中使用，公开了对常数操作数进行编码的系统和方法。 该系统包括能够产生短常数操作数和长常数操作数的恒定发电机单元。 常数发生器单元从指令音节中提取短常量操作数的位，右对齐输出音节中的位。 对于长常数操作数，常数发生器单元从扩展音节从指令音节和T高位比特提取K个低位比特。 右对齐K低位位和T高位位组合以表示一个输出音节中的长常数操作数。 响应于位于恒定生成指令内的操作码位的状态，常数发生器单元启用和禁用多路复用器自动生成适当的短或长常数操作数。

公开(公告)号：US06911869B2

公开(公告)日：2005-06-28

申请号：US10761760

申请日：2004-01-21

Applicant: Srikanth R. Muroor

Inventor： Srikanth R. Muroor

IPC: H03K3/0231 ,  H03L7/099 ,  H03L7/00

CPC classification number: H03L7/099 ,  H03K3/0231

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage. The VCO also comprises: 3) a constant charge current source for injecting the constant charge current into the storage capacitor when the comparator output rises to the positive saturation voltage; and 4) a constant discharge current source for draining the constant discharge current from the storage capacitor when the comparator output drops to the negative saturation voltage.

Abstract translation: 公开了一种压控振荡器（VCO），其接收+ V（IN）和-V（IN）控制电压，并且输出具有由+ V（IN）和-V（IN）控制确定的振荡频率的VCO输出信号 电压。 该VCO包括：1）通过恒定充电电流线性地充电并通过恒定放电电流线性放电的存储电容器; 2）用于将存储电容器电压与上阈值电压和较低阈值电压进行比较的比较器。 当存储电容器电压下降到低于下限值时，当存储电容器电压上升到高于阈值电压并上升到正饱和电压（+ V（SAT））时，比较器输出下降到负饱和电压（-V（SAT）） 阈值电压。 VCO还包括：3）恒定的充电电流源，用于当比较器输出上升到正饱和电压时，将恒定的充电电流注入到存储电容器中; 以及4）恒定放电电流源，用于当比较器输出下降到负饱和电压时从存储电容器排出恒定的放电电流。

公开(公告)号：US06903616B2

公开(公告)日：2005-06-07

申请号：US10603238

申请日：2003-06-24

Applicant: Rong Yin ,  Mehdi Zamanian

Inventor： Rong Yin ,  Mehdi Zamanian

IPC: H03B5/06 ,  H03B5/36 ,  H03B1/00

CPC classification number: H03B5/36 ,  H03B5/06

Abstract: A method and circuit are disclosed for enabling an oscillator circuit to oscillate a predetermined period of time following completion of a power-up operation. The circuit may include a counter having a control for receiving a control signal from a system power-on-reset circuit, and a clock input. A ring oscillator has an output coupled to the clock input of the counter.

Abstract translation: 公开了一种方法和电路，用于使振荡器电路能够在上电操作完成之后的预定时间段内振荡。 电路可以包括具有用于从系统上电复位电路接收控制信号的控制器和时钟输入的计数器。 环形振荡器具有耦合到计数器的时钟输入的输出。

公开(公告)号：US06898613B1

公开(公告)日：2005-05-24

申请号：US09383478

申请日：1999-08-26

Applicant: Steven R. Robinson ,  William A. Chren, Jr.

Inventor： Steven R. Robinson ,  William A. Chren, Jr.

IPC: G06F5/01 ,  G06F7/38 ,  G06F7/72

CPC classification number: G06F7/729 ,  G06F5/01

Abstract: A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.