公开(公告)号：US20060105574A1

公开(公告)日：2006-05-18

申请号：US11280186

申请日：2005-11-16

Applicant: Samantha Regini ,  Simone Alba

Inventor： Samantha Regini ,  Simone Alba

IPC: H01L21/461 ,  C23F1/00 ,  H01L21/302

CPC classification number: H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139

Abstract: A process for the definition of integrated circuits on a wafer having at least one silicon semiconductor layer includes masking the wafer with a photoresist layer. The process includes a development step of the photoresist with definition of a lithographic pattern, a hardening step of the photoresist with a plasma of inert gas, and a dry etching step with a plasma of reactive gas for transferring the lithographic pattern on the wafer. The dry etching step includes at least an initial step, or breakthrough, with a plasma of a chlorinated gas and of an inert gas for removal of a silicon native oxide grown on the wafer.

Abstract translation: 用于在具有至少一个硅半导体层的晶片上定义集成电路的方法包括用光致抗蚀剂层掩蔽晶片。 该方法包括具有光刻图案定义的光致抗蚀剂的显影步骤，具有惰性气体等离子体的光致抗蚀剂的硬化步骤以及用于将平版印刷图案转印到晶片上的反应气体等离子体的干蚀刻步骤。 干蚀刻步骤至少包括用氯化气体的等离子体和用于去除在晶片上生长的硅自然氧化物的惰性气体的初始步骤或穿透。

公开(公告)号：US20060087567A1

公开(公告)日：2006-04-27

申请号：US11252376

申请日：2005-10-18

Applicant: Mirko Guarnera ,  Giuseppe Messina ,  Valeria Tomaselli

Inventor： Mirko Guarnera ,  Giuseppe Messina ,  Valeria Tomaselli

IPC: H04N9/73

CPC classification number: H04N9/045 ,  H04N2209/045 ,  H04N2209/046

Abstract: Color image signals, as derived, e.g., by interpolating the output from a color filter array are arranged in pixels, each pixel having associated detected color information for a first color as well as undetected filled-in color information for at least a second and a third color. The images are thus exposed to false color and zipper effect artifacts, and are subject to processing preferably including the steps of: checking the images for the presence of zipper effect artifacts, and i) if said checking reveals the presence of zipper effect artifacts, applying a zipper effect removal process to said image signals; ii) if said checking fails to reveal the presence of zipper effect artifacts, applying a false color removal process to said image signals. False color and zipper effect artifacts are thus preferably both reduced by adaptively using the zipper effect removal process and the false color removal process.

Abstract translation: 例如，通过内插来自滤色器阵列的输出的彩色图像信号以像素排列，每个像素具有用于第一颜色的相关联的检测到的颜色信息以及未检测到的至少第二和第二颜色的填充颜色信息 第三色。 因此，图像暴露于假色和拉链效果伪像，并且经受处理优选包括以下步骤：检查图像中是否存在拉链效果伪像，以及i）如果所述检查显示出拉链效应伪像的存在，则应用 对所述图像信号的拉链效应去除处理; ii）如果所述检查不能揭示拉链效应伪像的存在，则对所述图像信号应用假色去除处理。 因此，优选通过自适应地使用拉链效果去除处理和假颜色去除处理来减少假色和拉链效果伪影。

公开(公告)号：US20060071242A1

公开(公告)日：2006-04-06

申请号：US11235495

申请日：2005-09-26

Applicant: Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri

Inventor： Ferruccio Frisina ,  Giuseppe Ferla ,  Angelo Magri

IPC: H01L29/768

CPC classification number: H01L29/66666 ,  H01L21/26586 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/41716 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7322 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/8611

Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas, realized in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be realized by a first metallization level. The gate, source and drain terminals or pads may be realized by a second metallization level. The device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area, and separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge. A sinker structure extends perpendicularly to the substrate and may be formed by a grid of sinkers located below both the first parallel regions and the second closed region to favor a conductive channel for a current coming from the source area and directed towards the drain area across the substrate.

Abstract translation: 垂直导电电子功率器件包括在布置在半导体衬底上的外延层中实现的相应的栅极，源极和漏极区域。 相应的栅极，源极和漏极金属化可以通过第一金属化水平来实现。 栅极，源极和漏极端子或焊盘可以通过第二金属化水平来实现。 该装置被配置为一组彼此平行延伸的模块化区域，每个模块区域具有由狭窄的栅极区域周边围绕的矩形细长源区域，并且彼此分开，其中漏区域在相对端平行延伸并连接 其具有形成装置外周边缘的第二封闭区域。 沉降片结构垂直于衬底延伸，并且可以由位于第一平行区域和第二闭合区域下方的沉陷片形成，以便有助于来自源区域的电流的导电通道，并且引导通过漏极区域 基质。

公开(公告)号：US20060028891A1

公开(公告)日：2006-02-09

申请号：US11197910

申请日：2005-08-05

Applicant: Carolina Selva ,  Rita Zappa ,  Danilo Rimondi ,  Cosimo Torelli ,  Giovanni Mastrodomenico

Inventor： Carolina Selva ,  Rita Zappa ,  Danilo Rimondi ,  Cosimo Torelli ,  Giovanni Mastrodomenico

IPC: G11C7/00

CPC classification number: G11C29/44 ,  G11C29/16 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/1806 ,  G11C2029/3602

Abstract: A self diagnosis (BISD) device for a random memory array, preferably integrated with the random access memory, executes a certain number of predefined test algorithms and identifies addresses of faulty locations. The BISD device recognizes certain fail patterns of interest and generates bit-strings corresponding to them. In practice, the BISD device may diagnose memory arrays and allow the identification of defects in the production process that affect a new technology during its learning phase, thus accelerating its maturation.

公开(公告)号：US20060023531A1

公开(公告)日：2006-02-02

申请号：US11194739

申请日：2005-08-01

Applicant: Luca Crippa ,  Rino Micheloni

Inventor： Luca Crippa ,  Rino Micheloni

IPC: G11C7/00

CPC classification number: G11C11/5642 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

Abstract: A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first circuit branch is coupled to a memory cell to be sensed so as to be run through by a current corresponding to a memory cell state. The feedback-controlled circuit element controls a memory cell access voltage, and the current-to-voltage conversion circuit converts the current into a corresponding converted voltage signal that is indicative of the memory cell state. The comparator compares the converted voltage signal with a comparison voltage for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element. Also provided is a method of sensing a memory cell.

Abstract translation: 提供感测电路用于感测半导体存储单元。 感测电路包括至少一个第一电路支路，第一电路支路中的反馈控制电路元件，第一支路中的电流 - 电压转换电路和至少一个比较器。 第一电路分支耦合到待感测的存储器单元，以便通过对应于存储单元状态的电流运行。 反馈控制电路元件控制存储单元访问电压，并且电流 - 电压转换电路将电流转换成指示存储单元状态的对应的转换电压信号。 比较器将转换的电压信号与比较电压进行比较，以便在存储单元的至少两个不同状态之间进行区分。 转换后的电压信号对应于反馈控制电路元件的控制信号。 还提供了一种感测存储器单元的方法。

公开(公告)号：US20060018159A1

公开(公告)日：2006-01-26

申请号：US11183229

申请日：2005-07-14

Applicant: Massimiliano Picca ,  Stefano Zanardi

Inventor： Massimiliano Picca ,  Stefano Zanardi

IPC: G11C16/04

CPC classification number: G11C29/82 ,  G11C29/76

Abstract: An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and each memory block including a plurality of memory pages; means for receiving an address corresponding to a respective memory block; selecting means for selecting the addressed memory block; and means for detecting a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers, each register corresponding to a respective memory block and storing an indication of the failure of the respective memory block; and means for reading the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

Abstract translation: 一种电可编程存储器，包括：相应地排列到NAND架构的多个存储单元的阵列，所述存储器单元分组成多个存储块，每个存储块包括多个存储器页; 用于接收对应于相应存储块的地址的装置; 选择装置，用于选择寻址的存储块; 以及用于检测寻址的存储块的故障的装置，其中用于检测故障的装置包括：多个寄存器，每个寄存器对应于相应的存储器块，并存储各个存储块的故障的指示; 以及用于响应于所述地址的接收而读取对应于所寻址的存储器块的寄存器的装置，并且其中所述可编程存储器还包括至少一个包括多个冗余存储器页的存储器单元的冗余存储器块，所述选择装置选择 至少一个冗余存储器块代替所寻址的存储器块，以响应读取故障指示。

公开(公告)号：US20060008084A1

公开(公告)日：2006-01-12

申请号：US11175978

申请日：2005-07-06

Applicant: Joan Daemen ,  Gilles Van Assche ,  Guido Bertoni

Inventor： Joan Daemen ,  Gilles Van Assche ,  Guido Bertoni

IPC: H04K1/00

CPC classification number: G06F21/85 ,  G06F12/1408 ,  G06F21/6209 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L2209/12

Abstract: A method and an element for ciphering with an integrated processor data to be stored in a memory, including applying to each data block to be ciphered a ciphering algorithm which is a function of at least one key specific to the integrated circuit, and before applying the ciphering algorithm thereto, combining the data block to be ciphered with the result of a function of the storage address of the ciphered block in the memory, and/or of combining the key with the result of a function of the storage address of the ciphered block in the memory and of a digital quantity different from the ciphering key.

Abstract translation: 一种用于使用要存储在存储器中的集成处理器数据进行加密的方法和元件，包括应用到要加密的每个数据块，加密算法，其是集成电路特有的至少一个密钥的函数，并且在应用 将加密的数据块与存储器中的加密块的存储地址的功能的结果组合，和/或将密钥与加密块的存储地址的功能的结果组合 在存储器中和与加密密钥不同的数字量。

公开(公告)号：US20050207497A1

公开(公告)日：2005-09-22

申请号：US11084503

申请日：2005-03-18

Applicant: Fabrizio Rovati ,  Luigi Della Torre ,  Luca Celetto ,  Andrea Vitali

Inventor： Fabrizio Rovati ,  Luigi Della Torre ,  Luca Celetto ,  Andrea Vitali

IPC: H04N7/12 ,  H04N7/24 ,  H04N7/26 ,  H04N19/89

CPC classification number: H04N21/2662 ,  H04N19/39 ,  H04N19/436 ,  H04N19/587 ,  H04N19/59 ,  H04N19/61 ,  H04N21/234327

Abstract: The method is directed to encoding/decoding a video signal sequence by generating therefrom multiple description subsequences wherein the subsequences are produced by a plurality of parallel video encoding processes based on respective encoding parameters. The method includes the step of commonly controlling the encoding/decoding parameters for the plurality of video encoding/decoding processes.

Abstract translation: 该方法涉及通过从其生成多个描述子序列对视频信号序列进行编码/解码，其中基于相应的编码参数由多个并行视频编码处理产生子序列。 该方法包括对多个视频编码/解码处理共同控制编码/解码参数的步骤。

公开(公告)号：US20050201756A1

公开(公告)日：2005-09-15

申请号：US11067461

申请日：2005-02-25

Applicant: Alessandro Inglese ,  Edmondo Gangi ,  Giuseppe Rotondo ,  Gaetano Di Stefano

Inventor： Alessandro Inglese ,  Edmondo Gangi ,  Giuseppe Rotondo ,  Gaetano Di Stefano

IPC: G08C23/04 ,  H04B10/00 ,  H04L27/00

CPC classification number: G08C23/04 ,  H04L27/00

Abstract: Transmitter device including a modulator apparatus for the generation of a modulated digital signal in a remote control system. The modulated signal is defined by at least one characteristic quantity correlated to an information to transmit. The modulator apparatus is characterized by including a finite states machine for generating a modulating digital signal to combine with a carrier signal and obtain the modulated signal. The finite states machine generates the modulating signal on the basis of digital data corresponding to said at least one characteristic quantity.

Abstract translation: 发射机装置包括用于在遥控系统中产生调制数字信号的调制器装置。 调制信号由与要发送的信息相关联的至少一个特征量定义。 调制器装置的特征在于包括一个有限状态机，用于产生调制数字信号以与载波信号组合并获得调制信号。 有限状态机根据对应于所述至少一个特征量的数字数据产生调制信号。

公开(公告)号：US20050195654A1

公开(公告)日：2005-09-08

申请号：US11067478

申请日：2005-02-25

Applicant: Antonino Conte ,  Mario Micciche ,  Alberto Di Martino ,  Alfredo Signorello

Inventor： Antonino Conte ,  Mario Micciche ,  Alberto Di Martino ,  Alfredo Signorello

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/16 ,  G11C16/34

Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.

Abstract translation: 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。