公开(公告)号：US11196428B1

公开(公告)日：2021-12-07

申请号：US17076200

申请日：2020-10-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Yoni Yosef-Hay ,  Ulrik Wismar

IPC: H03L7/099 ,  H03L7/081 ,  H03K3/037 ,  H03K3/017 ,  H03L7/187

Abstract: A Quadrature Voltage Controlled Oscillator (Quad VCO) based on standard digital cells and delay cells, is adapted to generate two high-frequency output signals that are “in quadrature”, so they both oscillate with similar frequency while exhibiting a mutual phase offset of about 90 degrees, and a) the digital cells include a mix of digital circuits used for implementing standard flip-flop circuits and standard logic gates; and b) the delay cells include circuits accepting a logic signal at their input and outputting a time-delayed version of said input signal, with a time delay that may be varied by a control voltage analog signal that determines the cell delay.

公开(公告)号：US11191197B2

公开(公告)日：2021-11-30

申请号：US16521607

申请日：2019-07-25

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avner Badihi ,  Pavel Vilner ,  Inbar Gozlan ,  Amir Pinhasovich

IPC: C09D5/32 ,  H05K9/00 ,  C09D7/61 ,  C09D175/04

Abstract: A method, system and paint for suppressing emission of high frequency electromagnetic radiation from an electronic system, the electronic system including at least one power supply unit, at least one printed circuit board (PCB) and at least one integrated circuit are provided. The method includes providing an electrically conductive housing configured to accommodate and encase the electronic system, the housing having an inner conductive surface, and applying a layer of an electromagnetic absorbing paint to the inner conductive surface of the housing to substantially cover the inner surface by the layer, the electromagnetic absorbing paint comprises a liquid matrix and an electromagnetic absorbing material.

公开(公告)号：US11171816B2

公开(公告)日：2021-11-09

申请号：US16943615

申请日：2020-07-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Matan Groen ,  Chen Gaist ,  Hananel Faig

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

公开(公告)号：US11165224B2

公开(公告)日：2021-11-02

申请号：US16015533

申请日：2018-06-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Itshak Kalifa ,  Elad Mentovich ,  Sylvie Rockman

IPC: H01S5/042 ,  H01S5/183 ,  H01S5/00 ,  G01R31/44 ,  G01R31/26 ,  H01S5/062 ,  H01S5/42 ,  H01S5/02345

Abstract: A layout for a vertical-cavity surface-emitting laser (VCSEL) is provided. In an example embodiment, the layout comprises a VCSEL, an etched shape around a mesa of the VCSEL, a signal contact layer deposited on section of the mesa, and a ground contact layer. The ground contact layer comprises three parts and is positioned around a first section of the etched shape. The first part of the ground contact layer is deposited on a second section of the etched shape. The second and third parts of the ground contact layer comprise two legs off of the first part. The two legs are symmetrically positioned about two sides of the signal contact layer to form a ground-signal-ground configuration.

公开(公告)号：US20210311266A1

公开(公告)日：2021-10-07

申请号：US16928037

申请日：2020-07-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dimitrios Kalavrouziotis ,  Donald Becker ,  Boaz Atias ,  Paraskevas Bakopoulos ,  Elad Mentovich

IPC: G02B6/42 ,  G02B6/02 ,  G02B6/38 ,  H04B10/25

Abstract: A network device includes an enclosure, a multi-chip module (MCM), an optical-to-optical connector, and a multi-core fiber (MCF) interconnect. The enclosure has a panel. The MCM is inside the enclosure. The optical-to-optical connector, which is mounted on the panel of the enclosure, is configured to transfer a plurality of optical communication signals. The MCF interconnect has a first end coupled to the MCM and a second end connected to the optical-to-optical connector on the panel, for routing the plurality of optical communication signals between the MCM and the panel.

公开(公告)号：US11102129B2

公开(公告)日：2021-08-24

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/28 ,  H04L12/801 ,  H04L12/927 ,  H04L12/863 ,  H04L29/08 ,  H04L12/841

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US20210248274A1

公开(公告)日：2021-08-12

申请号：US16783237

申请日：2020-02-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Roman Manevich ,  Lidiya Ivanitskaya

IPC: G06F21/72 ,  G06F30/398

Abstract: An apparatus reads a chip design comprising first and second blocks corresponding to first and second hardware modules, nodes, and data path segments that each connect a pair of nodes or a node to a block. Tracing backward along data paths that terminate at the second block, the apparatus identifies a secure cone. The secure cone comprises secure path segments of the data paths terminating at the second block and corresponding nodes. The apparatus identifies data paths originating at the first block and that are at least partially within the secure cone and determines whether any terminate outside the secure cone. When none of the data paths originating at the first block terminate outside the secure cone, the apparatus verifies the chip design. When a data path originating at the first block terminates outside the secure cone, the apparatus determines that the chip design has a potential leak.

公开(公告)号：US20210243121A1

公开(公告)日：2021-08-05

申请号：US16780940

申请日：2020-02-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/741 ,  G06F13/42 ,  H04L29/06

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US20210235107A1

公开(公告)日：2021-07-29

申请号：US16775463

申请日：2020-01-29

Applicant: Mellanox Technologies, Ltd. ,  BEAMR IMAGING LTD.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Ohad Markus ,  Uri Gadot ,  Aviad Raveh ,  Tamar Shoham

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/177

Abstract: A video processor includes a memory and a processor. The processor is coupled to memory and is configured to store in the memory (i) multiple raw frames belonging to a Group of Pictures (GOP) to be processed, and (ii) one or more reference frames. The processor is further configured to select for multiple target blocks having a same block-location in respective raw frames associated with a common reference frame, a common search region in the common reference frame, and before selecting another search region, to apply at least two motion estimation operations using at least two of the target blocks and the common search region, to estimate respective at least two Motion Vectors (MVs).

公开(公告)号：US20210203610A1

公开(公告)日：2021-07-01

申请号：US17204968

申请日：2021-03-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08 ,  H04L12/851 ,  H04L12/413 ,  H04L12/00

Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.