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    INTEGRATED ULTRALONG TIME CONSTANT TIME MEASUREMENT DEVICE AND FABRICATION PROCESS
    471.
    发明申请
    INTEGRATED ULTRALONG TIME CONSTANT TIME MEASUREMENT DEVICE AND FABRICATION PROCESS 审中-公开

    公开(公告)号：US20200075506A1

    公开(公告)日：2020-03-05

    申请号：US16549000

    申请日：2019-08-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

    IPC: H01L23/00 ,  H01L27/01 ,  H01L21/70 ,  G04F1/00

    Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

    NON-VOLATILE MEMORY WITH DOUBLE CAPA IMPLANT
    473.
    发明申请
    NON-VOLATILE MEMORY WITH DOUBLE CAPA IMPLANT 审中-公开

    公开(公告)号：US20200035304A1

    公开(公告)日：2020-01-30

    申请号：US16048524

    申请日：2018-07-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois TAILLIET ,  Roberto SIMOLA

    IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11517

    Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

    TRANSACTION ROUTING FOR SYSTEM ON CHIP
    474.
    发明申请
    TRANSACTION ROUTING FOR SYSTEM ON CHIP 审中-公开

    公开(公告)号：US20200026679A1

    公开(公告)日：2020-01-23

    申请号：US16504794

    申请日：2019-07-08

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/18

    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.

    Frequency Adjustment of an NFC Circuit
    476.
    发明申请
    Frequency Adjustment of an NFC Circuit 审中-公开

    公开(公告)号：US20190386706A1

    公开(公告)日：2019-12-19

    申请号：US16554236

    申请日：2019-08-28

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Alexandre Tramoni

    IPC: H04B5/00

    Abstract: A near-field communication circuit includes an oscillating circuit having a controllable capacitor. A control circuit is coupled to the oscillating circuit to control the controllable capacitor. A battery is coupled to the control circuit to enable control when the near-field communication circuit is in a standby mode. The near-field communication circuit can be utilized by a mobile communication device.

    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE
    477.
    发明申请
    COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE 审中-公开

    公开(公告)号：US20190371805A1

    公开(公告)日：2019-12-05

    申请号：US16542511

    申请日：2019-08-16

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

    IPC: H01L27/11563 ,  H01L27/11536

    Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

    Integrated circuit chip stack
    479.
    发明授权
    Integrated circuit chip stack 有权

    公开(公告)号：US10473709B2

    公开(公告)日：2019-11-12

    申请号：US16125096

    申请日：2018-09-07

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Alexandre Sarafianos ,  Thomas Ordas

    IPC: H01L23/00 ,  G01R31/12 ,  G06K19/073 ,  H01L25/065 ,  G01R31/317 ,  H01L23/538

    Abstract: An integrated circuit chip stack includes a main integrated circuit chip and at least one auxiliary integrated circuit chip. The main integrated circuit chip contains circuit components to be protected. The auxiliary integrated circuit chip is mounted to a surface of the main integrated circuit chip and includes a metal plane connected to ground located opposite the circuit components to be protected. The auxiliary integrated circuit chip further includes at least one insulated conductive track forming a tight pattern opposite the circuit components to be protected. A detection circuit is connected to the at least one conductive track and is configured to detect interruption of the at least one insulated conductive track.

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