公开(公告)号：US20240313054A1

公开(公告)日：2024-09-19

申请号：US18183468

申请日：2023-03-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jianwei PENG ,  Hong Yu

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/6656 ,  H01L21/31144

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

公开(公告)号：US12087384B2

公开(公告)日：2024-09-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US12076692B1

公开(公告)日：2024-09-03

申请号：US18533316

申请日：2023-12-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Justin M. Weinstein

IPC: B01D53/90 ,  B01D53/86

CPC classification number: B01D53/90 ,  B01D53/8696 ,  B01D2251/102 ,  B01D2251/11 ,  B01D2257/2025 ,  B01D2257/2027 ,  B01D2257/2042 ,  B01D2257/2045 ,  B01D2257/2047 ,  B01D2257/406 ,  B01D2257/553 ,  B01D2257/556 ,  B01D2258/0216

Abstract: A system to abate an emission from a first semiconductor process is disclosed. The system includes an abatement apparatus, such as a gas scrubber, to remove hazardous and toxic gas species from the emission. The abatement apparatus may combust the emission to remove these gas species using a fuel and oxidant. The system includes a fuel assembly fluidly coupled to the abatement apparatus which transmits the fuel from at least one source through the abatement apparatus. The fuel assembly may include a supply tank which contains a volume of fuel, a recovery apparatus which recovers and contains a recovery volume of fuel from a second semiconductor process, and a mass flow controller which may transmit fuel from at least one of the supply tank and the recovery apparatus through the abatement apparatus.

公开(公告)号：US20240290879A1

公开(公告)日：2024-08-29

申请号：US18114313

申请日：2023-02-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  James A. Cooper ,  Hema Lata Rao Maddi

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L21/02337 ,  H01L29/401 ,  H01L29/511 ,  H01L29/517

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.

公开(公告)号：US20240275282A1

公开(公告)日：2024-08-15

申请号：US18166576

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. TRAN ,  Shivraj G. Dharne ,  Asif Iqbal

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/096 ,  H02M1/36

CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/096 ,  H02M1/36

Abstract: A reference circuit for an electronic device having a plurality of power supply voltages comprises a supply start-up circuit, a power-down start-up circuit, and a reference generating circuit. The supply start-up circuit comprising a resistive-capacitive (RC) circuit coupled between a first power supply voltage and a ground. The RC circuit includes a pulse node coupled between a first capacitor and a resistive element, and generates a power-up pulse signal at the pulse node. The power-down start-up circuit is powered by a second power supply voltage and comprises a pulse generation circuit that generates a first start-up signal. The reference generating circuit outputs a reference signal. The reference generating circuit exists a low-power mode when either of the power-up pulse signal and the first start-up signal is generated.

公开(公告)号：US20240274712A1

公开(公告)日：2024-08-15

申请号：US18109126

申请日：2023-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66734

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the trench. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.

公开(公告)号：US20240274161A1

公开(公告)日：2024-08-15

申请号：US18166544

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain

IPC: G11C5/14 ,  G01R19/165

CPC classification number: G11C5/147 ,  G01R19/16519

Abstract: Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.

公开(公告)号：US20240266422A1

公开(公告)日：2024-08-08

申请号：US18166041

申请日：2023-02-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L29/745

CPC classification number: H01L29/7455

Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

公开(公告)号：US20240264374A1

公开(公告)日：2024-08-08

申请号：US18105304

申请日：2023-02-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G02B6/122 ,  G02B6/136 ,  H01L23/38 ,  H01L23/48

CPC classification number: G02B6/1228 ,  G02B6/136 ,  H01L23/38 ,  H01L23/481 ,  G02B2006/12121

Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a substrate including a cavity, a thermoelectric device inside the cavity, and a chip disposed inside the cavity adjacent to the thermoelectric device. The thermoelectric device includes a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.