公开(公告)号：US07274055B2

公开(公告)日：2007-09-25

申请号：US11171097

申请日：2005-06-29

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract translation: 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US07226842B2

公开(公告)日：2007-06-05

申请号：US10780826

申请日：2004-02-17

Applicant: Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

Inventor： Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC: H01L21/20 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

Abstract translation: 在应变通道外延源/漏极晶体管中，载流子的迁移率可能会增加。 在去除离子注入的源极/漏极区之后，掺杂的硅材料可以被覆盖。 覆盖沉积在非源极/漏极区域和源极/漏极区域中形成晶体膜形成非晶态膜。 通过使用对非晶硅有选择性的蚀刻，可以去除非晶材料。 这可以避免与掺杂硅材料的选择性沉积相关的一些问题。

公开(公告)号：US20060197164A1

公开(公告)日：2006-09-07

申请号：US11408133

申请日：2006-04-20

Applicant: Nick Lindert ,  Anand Murthy ,  Justin Brask

Inventor： Nick Lindert ,  Anand Murthy ,  Justin Brask

IPC: H01L29/76 ,  H01L21/332

CPC classification number: H01L29/66628 ,  H01L29/66636

Abstract: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

公开(公告)号：US06949482B2

公开(公告)日：2005-09-27

申请号：US10731269

申请日：2003-12-08

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/00

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract translation: 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US20050179066A1

公开(公告)日：2005-08-18

申请号：US10780826

申请日：2004-02-17

Applicant: Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

Inventor： Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

Abstract translation: 在应变通道外延源/漏极晶体管中，载流子的迁移率可能会增加。 在去除离子注入的源极/漏极区之后，掺杂的硅材料可以被覆盖。 覆盖沉积在非源极/漏极区域和源极/漏极区域中形成晶体膜形成非晶态膜。 通过使用对非晶硅有选择性的蚀刻，可以去除非晶材料。 这可以避免与掺杂硅材料的选择性沉积相关的一些问题。

公开(公告)号：US20050145944A1

公开(公告)日：2005-07-07

申请号：US10745978

申请日：2003-12-24

Applicant: Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

Inventor： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L27/12

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract translation: 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US20050133832A1

公开(公告)日：2005-06-23

申请号：US10744195

申请日：2003-12-22

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

公开(公告)号：US20050012146A1

公开(公告)日：2005-01-20

申请号：US10917722

申请日：2004-08-12

Applicant: Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

Inventor： Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

Abstract translation: 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US06653700B2

公开(公告)日：2003-11-25

申请号：US10191118

申请日：2002-07-08

Applicant: Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

Inventor： Robert S. Chau ,  Jack Kavalieros ,  Anand Murthy ,  Brian Roberds ,  Brian S. Doyle

IPC: H01L2976

CPC classification number: H01L29/66772 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78654 ,  Y10S977/70 ,  Y10S977/721 ,  Y10S977/936

Abstract: A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.

Abstract translation: 一种新颖的晶体管结构及其制造方法。 根据本发明，晶体管包括具有第一表面的本征硅体。 在本征硅体的第一表面上形成栅极电介质。 栅极电极形成在栅极电介质上，其中栅电极在栅极电介质上包括中间间隙功函数膜。 一对源极/漏极区域形成在本征硅体的相对侧上。

公开(公告)号：US06235568B1

公开(公告)日：2001-05-22

申请号：US09235782

申请日：1999-01-22

Applicant: Anand Murthy ,  Chia-Hong Jan ,  Ebrahim Andideh ,  Kevin Weldon

Inventor： Anand Murthy ,  Chia-Hong Jan ,  Ebrahim Andideh ,  Kevin Weldon

IPC: H01L218238

CPC classification number: H01L29/41783 ,  H01L21/823814 ,  H01L21/823842

Abstract: The present invention describes an MOS device having deposited silicon regions and its a method of fabrication. In one embodiment of the present invention a substrate having a thin oxide layer formed on a silicon surface is heated and exposed to an ambient comprising germane (GeH4) to remove the thin oxide from the silicon surface. A silicon or silicon alloy film can then be deposited onto the silicon surface of the substrate.

Abstract translation: 本发明描述了一种具有沉积硅区域的MOS器件及其制造方法。 在本发明的一个实施方案中，将形成在硅表面上的薄氧化物层的衬底加热并暴露于包含锗烷（GeH 4）的环境中以从硅表面除去薄氧化物。 然后可以将硅或硅合金膜沉积到衬底的硅表面上。