公开(公告)号：US06366509B2

公开(公告)日：2002-04-02

申请号：US09764952

申请日：2001-01-16

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C29/832

摘要： A pair of coupling transistors are connected in series with isolation transistors in each of a plurality of column node circuits coupled to first and second arrays of memory cells arranged in rows and columns. The coupling transistors for the complimentary digit lines in each column node circuit are rendered non-conductive in the event memory cells connected to the coupling transistors through digit lines of the first and second array are defective. As a result, defective memory cells in the first and second arrays are isolated from sense amplifiers in the column node circuits so that the sense amplifiers cannot affect non-defective memory cells.

摘要翻译： 一对耦合晶体管与耦合到以行和列布置的第一和第二存储器单元阵列的多个列节点电路中的每一个中的隔离晶体管串联连接。 在通过第一和第二阵列的数字线连接到耦合晶体管的存储单元是有缺陷的情况下，每列列节点电路中的互补数字线的耦合晶体管变得不导通。 结果，第一和第二阵列中的有缺陷的存储单元与列节点电路中的读出放大器隔离，使得读出放大器不会影响无缺陷存储单元。

公开(公告)号：US06185136B2

公开(公告)日：2001-02-06

申请号：US09353575

申请日：1999-07-15

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C29/832

摘要： A pair of coupling transistors are connected in series with isolation transistors in each of a plurality of column node circuits coupled to first and second arrays of memory cells arranged in rows and columns. The coupling transistors for the complimentary digit lines in each column node circuit are rendered non-conductive in the event memory cells connected to the coupling transistors through digit lines of the first and second array are defective. As a result, defective memory cells in the first and second arrays are isolated from sense amplifiers in the column node circuits so that the sense amplifiers cannot affect non-defective memory cells.

公开(公告)号：US5949730A

公开(公告)日：1999-09-07

申请号：US135845

申请日：1998-08-18

申请人： Brian M. Shirley ,  Kevin G. Duesman

发明人： Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C11/4096

摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.

摘要翻译： 在基于直流偏置电流感测的动态随机存取存储器（DRAM）装置中，辅助触发器装置耦合到一对I / O DIGIT线，用于确保DIGIT线中的一个返回到尽可能低的电压 内存访问。 读出放大器耦合到I / O线，以便在存储单元访问之后放大出现在线路上的差分电压。 辅助触发器在同时直流偏置被去激活时，将电流从低电平吸收到地，有效地将其电压降低到近地，以允许行访问信号的更快释放。

公开(公告)号：US5907166A

公开(公告)日：1999-05-25

申请号：US852905

申请日：1997-05-08

申请人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

发明人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

IPC分类号： G11C11/401 ,  H01L23/50 ,  H01L23/528 ,  H01L27/10 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/1815

摘要： A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

公开(公告)号：US5774408A

公开(公告)日：1998-06-30

申请号：US790375

申请日：1997-01-28

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4097 ,  G11C8/00 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4097

摘要： A memory architecture, suitable for a dynamic random access memory (DRAM) reduces layout area by sharing sense amplifiers, and arranging sense amplifiers to minimize die area. The sense amplifiers, comprising N-sense and P-sense amplifiers, are laid out in a region between memory array portions having memory cells that are each coupled to a digit line in a plurality of alternatingly sequenced digit line pairs. Each region has one N-sense amplifier for every two digit line pairs, and one P-sense amplifier for each digit line pair. Each N-sense amplifier is shared between two memory array portions, and is separated from each by an NFET isolation switch. Each P-sense amplifier is neither shared between the two memory array portions, nor separated from its corresponding memory array portion by an NFET isolation switch.

摘要翻译： 适用于动态随机存取存储器（DRAM）的存储器架构通过共享读出放大器来减少布局面积，并布置读出放大器以使管芯面积最小化。 包括N感测和P读出放大器的读出放大器布置在具有存储单元的存储器阵列部分之间的区域中，每个存储单元各自耦合到多个交替排列的数字线对中的数字线。 每个区域对于每两位数字线对具有一个N检测放大器，每个数字线对具有一个P读出放大器。 每个N检测放大器在两个存储器阵列部分之间共享，并且由NFET隔离开关与每个N型放大器分开。 每个P读出放大器既不在两个存储器阵列部分之间共享，也不通过NFET隔离开关与其对应的存储器阵列部分分离。

公开(公告)号：US5708617A

公开(公告)日：1998-01-13

申请号：US790377

申请日：1997-01-28

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C7/06 ,  G11G7/02

CPC分类号： G11C7/06 ,  G11C7/065

摘要： A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

公开(公告)号：US5677878A

公开(公告)日：1997-10-14

申请号：US587472

申请日：1996-01-17

申请人： Brian M. Shirley ,  Kevin G. Duesman

发明人： Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.

摘要翻译： 在基于直流偏置电流感测的动态随机存取存储器（DRAM）装置中，辅助触发器装置耦合到一对I / O DIGIT线，用于确保DIGIT线中的一个返回到尽可能低的电压 内存访问。 读出放大器耦合到I / O线，以便在存储单元访问之后放大出现在线路上的差分电压。 辅助触发器在同时直流偏置被去除时被激活，将电流从低电平吸收到地，有效地将其电压降低到近地，以允许行访问信号的更快释放。

公开(公告)号：US20080177943A1

公开(公告)日：2008-07-24

申请号：US12069812

申请日：2008-02-12

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US07088604B2

公开(公告)日：2006-08-08

申请号：US09809586

申请日：2001-03-15

申请人： Brian M. Shirley ,  David R. Brown

发明人： Brian M. Shirley ,  David R. Brown

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C7/1042 ,  G11C7/065 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.

公开(公告)号：US06937536B2

公开(公告)日：2005-08-30

申请号：US10664182

申请日：2003-09-17

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/842

摘要： A fuse option for a dynamic random access memory (DRAM) is provided to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a DRAM. The fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.

摘要翻译： 提供用于动态随机存取存储器（DRAM）的保险丝选项，用于当存储器单元的冗余行已被选择使用时选择性地减慢行地址信号。 当冗余行用于替换DRAM制造过程中识别的有缺陷的行时，熔断器选项被烧毁。 熔丝耦合到具有已知延迟的延迟电路。 当检测到有缺陷的行之后熔断器熔断时，延迟电路与用于将行地址选择信号传播到适当行的电路的行地址选通（RAS）链的选定部分串联耦合。 这提供了与延迟电路不一致的行地址比较和覆盖电路所需的额外时间。