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公开(公告)号：US06242782B1
公开(公告)日：2001-06-05
申请号：US09124283
申请日：1998-07-29
IPC分类号： H01L2994
CPC分类号： H01L21/765 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/10805 , Y10T307/839
摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.
摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被交叉耦合以形成用于动态随机存取存储器件的读出放大器。
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公开(公告)号：US06475851B1
公开(公告)日：2002-11-05
申请号：US09124478
申请日：1998-07-29
IPC分类号： H01L218238
CPC分类号： H01L21/765 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/10805 , Y10T307/839
摘要： Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.
摘要翻译： 相邻的非相关场效应晶体管由半导体衬底中的均匀掺杂材料的单个连续层形成。 在有源层上形成绝缘层。 导电层中的多个栅极限定晶体管。 在一个栅极和参考电位之间形成连接，通过防止跨越其的载流子传输，形成跨过活性材料的非相关晶体管之间的边界。
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公开(公告)号：US5949730A
公开(公告)日：1999-09-07
申请号：US135845
申请日：1998-08-18
申请人： Brian M. Shirley , Kevin G. Duesman
发明人： Brian M. Shirley , Kevin G. Duesman
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/02 , G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096
摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.
摘要翻译： 在基于直流偏置电流感测的动态随机存取存储器（DRAM）装置中，辅助触发器装置耦合到一对I / O DIGIT线，用于确保DIGIT线中的一个返回到尽可能低的电压 内存访问。 读出放大器耦合到I / O线，以便在存储单元访问之后放大出现在线路上的差分电压。 辅助触发器在同时直流偏置被去激活时，将电流从低电平吸收到地，有效地将其电压降低到近地，以允许行访问信号的更快释放。
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公开(公告)号：US5677878A
公开(公告)日：1997-10-14
申请号：US587472
申请日：1996-01-17
申请人： Brian M. Shirley , Kevin G. Duesman
发明人： Brian M. Shirley , Kevin G. Duesman
CPC分类号： G11C7/1048
摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.
摘要翻译： 在基于直流偏置电流感测的动态随机存取存储器（DRAM）装置中，辅助触发器装置耦合到一对I / O DIGIT线，用于确保DIGIT线中的一个返回到尽可能低的电压 内存访问。 读出放大器耦合到I / O线，以便在存储单元访问之后放大出现在线路上的差分电压。 辅助触发器在同时直流偏置被去除时被激活，将电流从低电平吸收到地，有效地将其电压降低到近地，以允许行访问信号的更快释放。
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公开(公告)号：US6015729A
公开(公告)日：2000-01-18
申请号：US919849
申请日：1997-08-28
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysliicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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公开(公告)号：US5834820A
公开(公告)日：1998-11-10
申请号：US543160
申请日：1995-10-13
IPC分类号： H01L21/765 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L21/765 , H01L27/0207 , H01L27/088 , H01L27/10805 , H01L21/823481 , Y10T307/839
摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.
摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被交叉耦合以形成用于动态随机存取存储器件的读出放大器。
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公开(公告)号：US5796666A
公开(公告)日：1998-08-18
申请号：US831609
申请日：1997-04-10
申请人： Brian M. Shirley , Kevin G. Duesman
发明人： Brian M. Shirley , Kevin G. Duesman
CPC分类号： G11C7/1048
摘要： A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.
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公开(公告)号：US6124163A
公开(公告)日：2000-09-26
申请号：US459131
申请日：1999-12-10
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L21/283
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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公开(公告)号：US5739576A
公开(公告)日：1998-04-14
申请号：US539855
申请日：1995-10-06
IPC分类号： H01L21/02 , H01L27/06 , H01L27/105 , H01L29/92 , H01L29/00
CPC分类号： H01L27/105 , H01L27/0623 , H01L27/0629 , H01L28/40
摘要： A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
摘要翻译： 公开了一种多层去耦电容器结构，其具有在导电掺杂硅衬底中形成的一个电极的第一去耦电容器和由导电掺杂多晶硅制成的第二电极。 配置在第二电极上方的第三分支导电层与第三层上方的第四导电层结合形成第二和第三去耦电容器。 第一去耦电容器用于去耦合与动态随机存取存储器单元相关的电路，而第二和第三去耦电容器为进一步的电路提供去耦。
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10.发明申请RANDOM ACCESS MEMORY DEVICE UTILIZING A VERTICALLY ORIENTED SELECT TRANSISTOR 有权使用垂直方向的选择晶体管的随机存取存储器件公开(公告)号：US20100276742A1
公开(公告)日：2010-11-04
申请号：US12834382
申请日：2010-07-12
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： G11C11/404 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译： 存储器结构具有带有环形栅极区域的垂直取向的存取晶体管。 制造晶体管使得晶体管的沟道相对于衬底的表面向外延伸。 围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。 还可以实现埋置的环形位线。 在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。
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