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    WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME
    42.
    发明申请
    WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME 有权
    无线位线方案的写驱动电路

    公开(公告)号：US20090034348A1

    公开(公告)日：2009-02-05

    申请号：US12184321

    申请日：2008-08-01

    Applicant: Jong-hoon JUNG ,  Chan-ho Lee

    Inventor： Jong-hoon JUNG ,  Chan-ho Lee

    IPC: G11C7/12

    CPC classification number: G11C7/1078 ,  G11C7/1048 ,  G11C7/1096 ,  G11C7/12

    Abstract: A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver.

    Abstract translation: 一种半导体存储器的写入驱动器电路，用于提供一种未复位的位线方案，其减小了未变形的Y路径的高度，以便减小存储器中芯片的面积。 写入驱动器电路可以包括输入锁存电路，其响应于输入使能信号锁存输入数据; 第一写驱动器，响应于写使能信号接收从输入锁存电路输出的写数据，并将数据输出到位线; 以及第二写入驱动器，其响应于所述写入使能信号接收从所述输入锁存电路输出的写入数据的反向数据，并将数据输出到互补位线，其中所述第一和第二写入驱动器具有与非门类型结构 并用作写入驱动器和预充电驱动器。

    REACTION VESSEL AND REACTION DEVICE
    43.
    发明申请
    REACTION VESSEL AND REACTION DEVICE 有权
    反应容器和反应装置

    公开(公告)号：US20080241019A1

    公开(公告)日：2008-10-02

    申请号：US11877562

    申请日：2007-10-23

    Applicant: Sung-chul Lee ,  Ju-yong Kim ,  Yong-kul Lee ,  Man-seok Han ,  Jun-sic Kim ,  Chan-ho Lee ,  Jin-goo Ahn

    Inventor： Sung-chul Lee ,  Ju-yong Kim ,  Yong-kul Lee ,  Man-seok Han ,  Jun-sic Kim ,  Chan-ho Lee ,  Jin-goo Ahn

    IPC: B01J15/00 ,  B01J19/00

    CPC classification number: B01J19/249 ,  B01J23/40 ,  B01J2219/2455 ,  B01J2219/2459 ,  B01J2219/246 ,  B01J2219/2465 ,  B01J2219/2479 ,  B01J2219/2485

    Abstract: Provided is a reaction vessel for a fuel cell, and more particularly to a reaction vessel exhibiting improved thermal efficiency, and a reaction device for a steam reforming reaction for a fuel cell. The reaction device includes a cylindrical reaction catalyst chamber on which a target reaction catalyst for a predetermined target reaction is disposed; and a tubular oxidation catalyst chamber surrounding the reaction catalyst chamber, comprising an oxidation reaction catalyst therein. The reaction device according features an increased contact area between catalyst and gas, and rapidly heating of the gas in contact with the catalyst to a desired reaction temperature.

    Abstract translation: 提供一种用于燃料电池的反应容器，更具体地说，涉及一种表现出改善的热效率的反应容器，以及用于燃料电池的蒸汽重整反应的反应装置。 反应装置包括：圆筒状的反应催化剂室，配置有用于规定的目标反应的目标反应催化剂; 以及围绕反应催化剂室的管状氧化催化剂室，其中包含氧化反应催化剂。 反应装置的特征在于催化剂和气体之间的接触面积增加，并且将与催化剂接触的气体快速加热到所需的反应温度。

    Semiconductor memory device with shift redundancy circuits
    46.
    发明授权
    Semiconductor memory device with shift redundancy circuits 有权
    具有移位冗余电路的半导体存储器件

    公开(公告)号：US07355910B2

    公开(公告)日：2008-04-08

    申请号：US11337493

    申请日：2006-01-24

    Applicant: Chan-Ho Lee ,  Jeung-Joo Lim ,  Eun-Kyoung Lim

    Inventor： Chan-Ho Lee ,  Jeung-Joo Lim ,  Eun-Kyoung Lim

    IPC: G11C7/00

    CPC classification number: G11C17/165 ,  G11C17/18 ,  G11C29/027 ,  G11C29/848

    Abstract: A semiconductor memory device including a shift redundancy circuit with two buffer chains, two fuses connected to the shift redundancy circuit, a plurality of fuse cut-out detecting circuits for detecting cut-out status of the fuses, and two spare cell control circuits for controlling two spare memory cell rows, wherein word line control signals for controlling corresponding word lines connected to memory cells in a memory cell array are shifted upward and downward to control respective next word lines, thereby replacing two defective memory cell rows with the two spare memory cell rows.

    Abstract translation: 一种半导体存储器件，包括具有两个缓冲链的移位冗余电路，连接到移位冗余电路的两个熔丝，用于检测保险丝的断开状态的多个熔丝切断检测电路和用于控制的两个备用电池控制电路 两个备用存储单元行，其中用于控制连接到存储单元阵列中的存储器单元的对应字线的字线控制信号向上和向下移位以控制相应的下一个字线，由此用两个备用存储单元替换两个有缺陷的存储单元行 行。

    Fuel cell system using butane
    47.
    发明申请
    Fuel cell system using butane 有权
    燃料电池系统使用丁烷

    公开(公告)号：US20070166579A1

    公开(公告)日：2007-07-19

    申请号：US11651101

    申请日：2007-01-09

    Applicant: Ju Yong Kim ,  Sung Chul Lee ,  Chan Ho Lee ,  Dong Myung Suh ,  Jin Goo Ahn ,  Jin Kwang Kim ,  Dong Uk Lee

    Inventor： Ju Yong Kim ,  Sung Chul Lee ,  Chan Ho Lee ,  Dong Myung Suh ,  Jin Goo Ahn ,  Jin Kwang Kim ,  Dong Uk Lee

    IPC: H01M8/06 ,  H01M8/04 ,  H01M8/10

    CPC classification number: H01M8/04164 ,  F17C2270/0763 ,  H01M8/04029 ,  H01M8/04074 ,  H01M8/04208 ,  H01M8/04291 ,  H01M8/0618 ,  H01M2008/1095 ,  Y02E60/321

    Abstract: A fuel cell system comprises: a fuel container for storing fuel liquefied with pressure; a reformer for generating hydrogen from the fuel through a catalyst reaction based on heat energy; an electric generator for generating electricity by transforming energy of an electrochemical reaction between hydrogen and oxygen into electric energy; a condenser for condensing water produced in the electric generator; and a heat exchanger passing through the condenser for cooling the condenser by latent heat of the fuel. With this configuration, cooling water cooled by latent heat of a fuel container is employed to cool the condenser without using a separate cooler. Furthermore, air is mixed with butane fuel without using a separate power unit, so that it is possible to achieve a more compact and highly efficient fuel cell.

    Abstract translation: 燃料电池系统包括：用于储存压力液化的燃料的燃料容器; 用于通过基于热能的催化剂反应从燃料产生氢的重整器; 通过将氢和氧之间的电化学反应的能量转化为电能来发电的发电机; 用于冷凝在发电机中产生的水的冷凝器; 以及通过冷凝器的热交换器，用于通过燃料的潜热冷却冷凝器。 采用这种结构，采用通过燃料容器的潜热冷却的冷却水来冷却冷凝器而不使用单独的冷却器。 此外，空气与丁烷燃料混合，而不使用单独的动力单元，使得可以实现更紧凑和高效的燃料电池。

    Semiconductor integrated circuit and method for detecting soft defects in static memory cell
    48.
    发明授权
    Semiconductor integrated circuit and method for detecting soft defects in static memory cell 失效
    用于检测静态存储单元中的软缺陷的半导体集成电路和方法

    公开(公告)号：US07232696B2

    公开(公告)日：2007-06-19

    申请号：US11058380

    申请日：2005-02-15

    Applicant: Chan-ho Lee

    Inventor： Chan-ho Lee

    IPC: H01L21/66 ,  G11C7/00

    CPC classification number: G11C29/52 ,  G11C11/41 ,  G11C2029/1204

    Abstract: Provided are a semiconductor integrated circuit including a unit which detects soft defects in a pull-up circuit of a static memory cell, and a soft defect detection method and a testing method thereof. The semiconductor integrated circuit includes a static memory cell, a bit line connected to a first node of the static memory cell and a complementary bit line connected to a second node of the static memory cell, and an equalization circuit connected to the bit line and the complementary bit line to equalize the bit line and the complementary bit line in response to a test signal during a test mode. The semiconductor integrated circuit and the soft defect detection method can rapidly detect soft defects in the pull-up circuit of the static memory cell without a retention test. Furthermore, the testing method can rapidly detect soft defects in the pull-up circuit of the static memory cell, allowing the test time to be drastically reduced.

    Abstract translation: 提供一种半导体集成电路，其包括检测静态存储单元的上拉电路中的软缺陷的单元，以及软缺陷检测方法及其测试方法。 半导体集成电路包括静态存储单元，连接到静态存储单元的第一节点的位线和连接到静态存储单元的第二节点的互补位线，以及连接到位线和 互补位线，以在测试模式期间响应于测试信号来均衡位线和互补位线。 半导体集成电路和软缺陷检测方法可以快速检测静态存储单元的上拉电路中的软缺陷，而无需保留测试。 此外，测试方法可以快速检测静态存储单元的上拉电路中的软缺陷，从而大大降低测试时间。

    MASK GUIDE
    50.
    发明公开
    MASK GUIDE 审中-公开

    公开(公告)号：US20230248089A1

    公开(公告)日：2023-08-10

    申请号：US18087293

    申请日：2022-12-22

    Applicant: Chan-Ho Lee

    Inventor： Chan-Ho Lee

    IPC: A41D13/11

    CPC classification number: A41D13/1169

    Abstract: There is provided a mask guide including a guide positioned between a mask and a chin of a user to prevent the user's chin and an inner surface of the mask from coming in contact with each other. The guide includes a first guide disposed on the inner surface of the mask. The guide includes a second guide configured to be positioned on the user's chin and configured to be moved in accordance with movement of the user's chin.

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