INTEGRATED CIRCUIT AND AN OPERATION METHOD THEREOF

    公开(公告)号:US20230253785A1

    公开(公告)日:2023-08-10

    申请号:US18303434

    申请日:2023-04-19

    CPC classification number: H02H9/046 H03K17/56

    Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

    INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME

    公开(公告)号:US20230089792A1

    公开(公告)日:2023-03-23

    申请号:US17508176

    申请日:2021-10-22

    Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

    Memory device
    47.
    发明授权

    公开(公告)号:US11514974B2

    公开(公告)日:2022-11-29

    申请号:US17208523

    申请日:2021-03-22

    Abstract: A memory device includes a word line driver. The word line driver is coupled through word lines to an array of bit cells. The word line driver includes a first driving circuit, a second driving circuit and a modulating circuit. The first driving circuit and the second driving circuit are configured to select a word line. The modulating circuit is coupled through the selected word line to the first driving circuit and the second driving circuit, and is configured to modulate at least one signal transmitted through the selected word line. The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions of the selected word line. The first voltage signal is substantially the same as the second voltage signal. A method is also disclosed herein.

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