公开(公告)号：US6085299A

公开(公告)日：2000-07-04

申请号：US974734

申请日：1997-11-19

申请人： Michael F. Angelo ,  Craig A. Miller ,  David R. Wooten

发明人： Michael F. Angelo ,  Craig A. Miller ,  David R. Wooten

IPC分类号： G06F1/00 ,  G06F11/00 ,  G06F12/14 ,  G06F21/00 ,  G06F12/16

CPC分类号： G06F21/56 ,  G06F11/004 ,  G06F21/572 ,  G06F12/1433 ,  G06F2211/1097

摘要： A secure start-up system for a computer enables a flash memory to be reset in a secured way. Various operations are carried out to make sure that the reset is an authorized one, and to avoid unauthorized, e.g. virus, infiltration. These operations include multiple tests to avoid the probability of the reset being unauthorized. Any one or more than one of the following can be used. Flashing is only authorized when a special flash enable bit is set in the non-volatile memory. This flash enable bit is reset during every startup cycle. Flashing is only authorized from a cold boot as opposed from a warm boot. This minimizes the possibility of a computer routine authorizing flashing by a software reset. Flashing is only authorized from a floppy. This prevents a virus from writing the flashing routine to the boot sector of a non-removable disc. The user is warned prior to flashing, and asked to confirm. Finally, contents of the flashing routine can be checked using some kind of checking algorithm such as a secure hash algorithm.

摘要翻译： 用于计算机的安全启动系统使得可以以安全的方式重置闪存。 执行各种操作以确保复位是授权的，并且避免未经授权的复位。 病毒，渗透。 这些操作包括多个测试，以避免重置未经授权的可能性。 可以使用以下任何一个或多于一个。 只有在非易失性存储器中设置了特殊闪光使能位时，闪存才被授权。 每个启动周期中，该闪存使能位都被复位。 闪电只能从冷启动授权，而不是热启动。 这样可以最大程度地减少计算机程序授权通过软件重置闪烁的可能性。 闪烁只能从软盘授权。 这样可以防止病毒将闪存例程写入不可移动光盘的引导扇区。 在闪烁之前警告用户，并要求确认。 最后，可以使用诸如安全散列算法的某种检查算法检查闪烁例程的内容。

公开(公告)号：US5832299A

公开(公告)日：1998-11-03

申请号：US882823

申请日：1997-06-26

申请人： David R. Wooten

发明人： David R. Wooten

IPC分类号： G06F9/455 ,  G06F12/02 ,  G06F13/10 ,  G06F12/10

CPC分类号： G06F9/45533 ,  G06F12/0292 ,  G06F13/105 ,  G06F2212/206

摘要： A processor having the prior three user addressing modes and a new virtual system mode (VSM). The user modes include real mode, protected mode and virtual 8086 mode. In VSM, the processor can utilize the VSM addressing mechanism and the mode of operation prior to entering VSM. Transitions from the user modes to virtual system mode can be made by indirect calls through a call gate or through vectored entries. While in VSM the processor can utilize VSM memory and I/O space modes, but can also directly utilize the I/O space and memory of the user mode present prior to entry into VSM by using a segment override. The upper 16 MB of the virtual system mode memory space (0xff000000 through 0xffffffff) is designated as non-mapped virtual system mode memory. Virtual system mode logical addresses below 0xff000000 will be translated to physical addresses by the current page table if paging is enabled (protected mode). Upon exiting VSM, any processor registers that were saved are restored so the user mode operation can continue as if the emulation operation were performed by the normal interrupt service routine.

摘要翻译： 具有先前三种用户寻址模式的处理器和新的虚拟系统模式（VSM）。 用户模式包括实模式，保护模式和虚拟8086模式。 在VSM中，处理器可以在进入VSM之前利用VSM寻址机制和操作模式。 从用户模式到虚拟系统模式的转换可以通过通过呼叫门或通过向量输入的间接呼叫进行。 在VSM中，处理器可以利用VSM存储器和I / O空间模式，但也可以通过使用段重写来直接利用在进入VSM之前存在的用户模式的I / O空间和存储器。 虚拟系统模式存储空间（0xff000000至0xffffffff）的高16 MB被指定为非映射虚拟系统模式存储器。 如果分页启用（保护模式），虚拟系统模式逻辑地址低于0xff000000将被当前页表转换为物理地址。 退出VSM后，任何已保存的处理器寄存器将被恢复，以便用户模式操作可以继续，仿佛仿真操作由正常中断服务程序执行。

公开(公告)号：US5819051A

公开(公告)日：1998-10-06

申请号：US578168

申请日：1995-12-29

申请人： David E. Murray ,  David R. Wooten

发明人： David E. Murray ,  David R. Wooten

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4295

摘要： A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.

公开(公告)号：US5687388A

公开(公告)日：1997-11-11

申请号：US986918

申请日：1992-12-08

申请人： David R. Wooten ,  Craig A. Miller ,  Kevin B. Leigh ,  Robert Brett Costley ,  Christopher E. Simonich

发明人： David R. Wooten ,  Craig A. Miller ,  Kevin B. Leigh ,  Robert Brett Costley ,  Christopher E. Simonich

IPC分类号： G06F13/40 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byte wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transferred in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.

摘要翻译： 用于计算机I / O子系统的点对点连接架构，从而产生可扩展的树结构。 主I / O集中器（MIOC）连接到主机总线，处理面向总线的结构与I / O子系统的树结构之间的转换。 远离主机总线的端口是下游端口，符合简单的字节宽消息协议。 各种IOC和设备可以连接到MIOC的下游端口之一。 MIOC根据地理寻址方案将传输指向适当的信道。 IOC连接充当分支的进一步点。 最终达到IOD或I / O设备，具有用于连接到IOC的上行端口和下游端口以及适用于特定外围设备的内部逻辑。 各种寄存器存在于IOC和IOD中，以允许确定拓扑和存在的特定设备。 消息和命令在I / O子系统中以定义的数据包传输。 使用各种读取，写入和交换命令，其中使用读取响应来允许拆分事务读取操作。 还存在某些状态和控制命令。 中断通过使中断电平对应于可编程中断控制器的存储器地址来处理，从而允许简单地选择要由器件产生的中断，而不需要单独的布线。

公开(公告)号：US5651130A

公开(公告)日：1997-07-22

申请号：US544109

申请日：1995-10-17

申请人： Lee B. Hinkle ,  Gary W. Thome ,  Paul A. Santeler ,  David R. Wooten ,  John A. Landry

发明人： Lee B. Hinkle ,  Gary W. Thome ,  Paul A. Santeler ,  David R. Wooten ,  John A. Landry

IPC分类号： G06F12/02 ,  G11C7/10 ,  G11C8/18 ,  G06F13/16

CPC分类号： G11C8/18 ,  G06F12/0215 ,  G11C7/1021

摘要： A memory controller dynamically predicts whether a next memory cycle which is not yet available will result in a page miss or page hit condition. RAS lines are selectively precharged if the next memory cycle is predicted to be a page miss. The memory controller keeps track of various combinations of types of cycles when a type of memory cycle is followed by a type of non-memory pending cycle. For each such combination, the memory controller determines the percentage of combinations which result in a page hit on the next memory cycle. Using this history, the memory controller selectively precharges the RAS lines when a certain combination of types of cycles indicates a percentage of hits is below a predicted threshold. If a number of page hits exceeds the predicted threshold, precharging is not performed.

摘要翻译： 存储器控制器动态地预测下一个不可用的存储器周期是否会导致页错失或页命中条件。 如果下一个存储周期被预测为页错，RAS线将被选择性地预充电。 当一种类型的非存储器未决循环之后，存储器控制器跟踪周期类型的各种组合。 对于每个这样的组合，存储器控制器确定在下一个存储周期中导致页命中的组合的百分比。 使用这个历史，存储器控制器当循环类型的某种组合指示命中的百分比低于预测阈值时选择性地预充电RAS线。 如果多次页面命中超过预测阈值，则不执行预充电。

公开(公告)号：US4431927A

公开(公告)日：1984-02-14

申请号：US256590

申请日：1981-04-22

申请人： Sargent S. Eaton, Jr. ,  David R. Wooten

发明人： Sargent S. Eaton, Jr. ,  David R. Wooten

IPC分类号： H03K19/096 ,  H03K5/02 ,  H03K17/06 ,  H03K19/017 ,  H03K17/12 ,  H03K5/135

CPC分类号： H03K19/01735

摘要： A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.

摘要翻译： 描述了用于MOS时钟发生器的触发电路。 时钟发生器是使用耦合到控制晶体管的常规双自举电路来开发高电平时钟输出信号的类型。 触发电路预先控制晶体管，以促进适当的引导操作。 包括在触发电路中的是多个互连的晶体管，其响应于预充电信号，然后响应用于使控制晶体管关闭的预热信号，然后用于在控制晶体管的电极处建立选定的电位，以便先决条件用于自举。 响应于随后的触发信号，触发电路使得控制晶体管能够开发高电平时钟输出信号。

公开(公告)号：US4344156A

公开(公告)日：1982-08-10

申请号：US195729

申请日：1980-10-10

申请人： Sargent S. Eaton, Jr. ,  David R. Wooten

发明人： Sargent S. Eaton, Jr. ,  David R. Wooten

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C7/1033 ,  G11C8/04

摘要： A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

摘要翻译： 描述了一种在半导体存储器中用于在多个连续存储器位置和数据输出总线之间快速传送数据的系统。 该系统包括多个数据锁存器，用于存储从存储器中的连续位置导出的数据，以及相应的多个串行耦合解码器，每个解码器与数据锁存器之一相关联。 响应于地址输入，一个解码器被使能以使其相关联的数据锁存器将其存储的数据输出到数据总线。 后一个解码器然后禁用自身并启用下一个解码器，使得第二个锁存器输出其存储的数据。 该过程继续，每个解码器禁用自身并启用下一个解码器，使得数据锁存器被依次输出其存储的数据。