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公开(公告)号：US4389715A
公开(公告)日：1983-06-21
申请号：US194613
申请日：1980-10-06
CPC分类号： G11C29/808
摘要： A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective main memory cells.
摘要翻译： 描述了用于用备用存储器单元替换动态RAM中的有缺陷的主存储器单元的冗余方案。 备用单元被布置成存储器单元的备用行和备用列的组，使得多组备用行和单元列被替换有缺陷的主行和单元列，以便修复相对较大的相邻行的缺陷 和主存储单元的列。 在优选实施例中，RAM包括多个地址缓冲器，每个地址缓冲器接收输入行地址位，然后接收输入列地址位，用于顺序地输出行和列地址数据。 与每个缓冲器相关联的是存储缺陷行地址，存储有缺陷列地址和比较器的存储。 存储器保持缺陷的存储单元地址，比较器顺序地与由缓冲器顺序输出的地址数据进行比较。 当比较器感测到匹配时，产生控制信号以启动用于缺陷主存储器单元的备用存储器单元的替换。
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公开(公告)号：US4351034A
公开(公告)日：1982-09-21
申请号：US195728
申请日：1980-10-10
IPC分类号： G11C11/419 , G11C11/401 , G11C11/409 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4097 , G11C11/409 , G11C11/4091
摘要： A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines. After the logic state is read, the selecting circuit enables the memory cell capacitor to be refreshed for further sensing by the sense amplifier.
摘要翻译： 描述折叠的位线共享读出放大器装置，用于感测动态MOS随机存取存储器中访问的存储器单元的逻辑状态。 在优选实施例中，共享读出放大器位于第一和第二隔离晶体管之间并且耦合到第一和第二位线。 相同的共享读出放大器也位于第三和第四隔离晶体管之间并且耦合到第三和第四位线。 当要访问的存储器单元的状态时，其存储单元电容器被耦合到所选位线，并且虚设单元电容器耦合到与选定位线相邻的位线。 解码电路选择性地激活共享读出放大器以感测所选位线与其相邻位线之间的电压差，以便确定与所访问的存储器单元相关联的逻辑状态。 然后，读出放大器锁存到该逻辑状态，以便通过输入/输出总线进行读取。 在读取逻辑状态之后，选择电路使存储单元电容器被刷新以便由读出放大器进一步感测。
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公开(公告)号：US4431927A
公开(公告)日：1984-02-14
申请号：US256590
申请日：1981-04-22
IPC分类号： H03K19/096 , H03K5/02 , H03K17/06 , H03K19/017 , H03K17/12 , H03K5/135
CPC分类号： H03K19/01735
摘要： A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate proper bootstrapping operation. Included in the trigger circuit is a plurality of interconnected transistors which respond to a pre-charge signal and then a warmup signal for turning the control transistor off and then for establishing selected potentials at the electrodes of the control transistor to precondition it for bootstrapping. In response to a subsequent trigger signal, the trigger circuit enables the control transistor for developing a high level clock output signal.
摘要翻译： 描述了用于MOS时钟发生器的触发电路。 时钟发生器是使用耦合到控制晶体管的常规双自举电路来开发高电平时钟输出信号的类型。 触发电路预先控制晶体管，以促进适当的引导操作。 包括在触发电路中的是多个互连的晶体管，其响应于预充电信号，然后响应用于使控制晶体管关闭的预热信号，然后用于在控制晶体管的电极处建立选定的电位，以便先决条件用于自举。 响应于随后的触发信号，触发电路使得控制晶体管能够开发高电平时钟输出信号。
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公开(公告)号：US4344156A
公开(公告)日：1982-08-10
申请号：US195729
申请日：1980-10-10
CPC分类号： G11C8/10 , G11C7/1033 , G11C8/04
摘要： A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches. In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch outputs its stored data. The process continues with each decoder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.
摘要翻译： 描述了一种在半导体存储器中用于在多个连续存储器位置和数据输出总线之间快速传送数据的系统。 该系统包括多个数据锁存器，用于存储从存储器中的连续位置导出的数据，以及相应的多个串行耦合解码器，每个解码器与数据锁存器之一相关联。 响应于地址输入，一个解码器被使能以使其相关联的数据锁存器将其存储的数据输出到数据总线。 后一个解码器然后禁用自身并启用下一个解码器，使得第二个锁存器输出其存储的数据。 该过程继续，每个解码器禁用自身并启用下一个解码器，使得数据锁存器被依次输出其存储的数据。
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5.发明授权Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits 失效降低CMOS集成电路闭锁敏感性的方法和装置
公开(公告)号：US4571505A
公开(公告)日：1986-02-18
申请号：US552249
申请日：1983-11-16
IPC分类号： H01L27/04 , G05F3/20 , G11C11/407 , H01L21/822 , H01L27/08 , H01L27/092 , H03K19/003 , H03K17/693
CPC分类号： H03K19/00315 , G05F3/205 , H01L27/0921
摘要： Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. The charge pump, clamping transistor and related elements are on the same CMOS substrate where latch-up is to be controlled. The substrate to ground capacitance of the substrate is increased to prevent localized substrate voltage disturbances which may induce latch-up.
摘要翻译： 用于控制CMOS电路中的闩锁的方法和装置感测电源转换，响应于感测电源转换而将衬底钳位到地，并且在电源转换之后释放钳位。 电荷泵将衬底泵送至-3伏。 电荷泵，钳位晶体管和相关元件位于要控制闩锁的同一CMOS基板上。 衬底对衬底的接地电容增加，以防止局部衬底电压干扰，这可能导致闩锁。
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公开(公告)号：US4354123A
公开(公告)日：1982-10-12
申请号：US66148
申请日：1979-08-13
IPC分类号： G06F1/26 , G06F1/04 , G11C5/00 , G11C11/4076 , H03K4/24
CPC分类号： G11C11/4076 , G11C5/00
摘要： A high voltage clock generator including an isolation and precharge circuit to charge a bootstrap capacitance at a time prior to driving the load capacitance to a higher voltage level. The first clock generator charges a load capacitance to the initial voltage level while the isolation precharge circuit has already acted to charge the bootstrap capacitance. A second clock generator drives the bootstrap capacitance to a higher voltage level, at which time the isolation precharge circuit acts to engage the bootstrap capacitance to the load capacitance and charge the load capacitance to a higher voltage level.
摘要翻译： 一种高电压时钟发生器，包括隔离和预充电电路，用于在将负载电容驱动到较高电压电平之前的时间对自举电容充电。 第一个时钟发生器将负载电容充电到初始电压电平，而隔离预充电电路已经用来对自举电容充电。 第二个时钟发生器将自举电容驱动到更高的电压电平，此时隔离预充电电路用于将自举电容与负载电容接合，并将负载电容充电到更高的电压电平。
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公开(公告)号：US4149232A
公开(公告)日：1979-04-10
申请号：US861452
申请日：1977-12-16
IPC分类号： H03K19/00 , H02M7/537 , H03K5/02 , H03K19/094 , H02M7/44
CPC分类号： H02M7/537
摘要： Voltage boosting circuits of a type using a plurality of inverters with parallelled inputs, each inverter arranged to pump charge into a respective pair of booster capacitors--rather than one respective booster capacitor--to develop an output voltage in each stage which is doubled in amplitude over the voltage used to power the inverter in that stage. To this end, the inverter in each successive stage of the voltage boosting circuit is powered by the output voltage of the preceding stage.
摘要翻译： 使用具有并联输入的多个反相器的类型的升压电路，每个反相器布置成将电荷泵送到相应的一对升压电容器中，而不是一个相应的升压电容器，以在每个级中产生两倍的幅度的输出电压 在该阶段为逆变器供电的电压。 为此，升压电路的每个连续级中的逆变器由前级的输出电压供电。
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公开(公告)号：US4491936A
公开(公告)日：1985-01-01
申请号：US346605
申请日：1982-02-08
IPC分类号： G11C11/409 , G11C11/40 , G11C11/24
CPC分类号： G11C11/409
摘要： A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) and a decoded plate line (40). The plate line (40) receives a bi-level voltage which shifts levels in a timing sequence keyed to the word line (34) signal. Shifting of voltage levels provided to the capacitor (38) through the plate line (40) essentially doubles the signal margin of the memory circuit (30) to thereby enhance the reliability of the data stored in the memory circuit (30).
摘要翻译： 动态随机存取存储器单元（30）包括存取晶体管（32），其栅极端子连接到字线（34），其源极和漏极端子连接在位线（36）和节点（37）之间， 。 电池存储电容器（38）连接在节点（37）和解码板线（40）之间。 板线（40）接收双击电平，该双电平电压按照与字线（34）信号相关的定时序列移位电平。 通过板线（40）提供给电容器（38）的电压电平的移动基本上使存储电路（30）的信号余量加倍，从而增强存储在存储电路（30）中的数据的可靠性。
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公开(公告)号：US4363111A
公开(公告)日：1982-12-07
申请号：US194614
申请日：1980-10-06
IPC分类号： G11C11/401 , G11C11/4099 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4099
摘要： A dummy cell arrangement is described for sensing the logic state of an accessed memory cell in an MOS memory in which a memory cell capacitor of a given size is associated with each memory cell. In the preferred embodiment, a plurality of dummy cells are included, each of which has a dummy capacitor of substantially the same given size as a memory cell capacitor. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a bit line to change the voltage thereon and a selected dummy cell capacitor is coupled to a pair of bit lines so as to effect substantially equal transfers of charge between the dummy capacitor and the bit lines to which it is coupled. The resulting voltage on the memory cell capacitor's bit line is compared to the voltage on one of the dummy capacitor's bit lines so as to determine the logic state of the accessed memory cell.
摘要翻译： 描述了用于感测MOS存储器中的存取存储器单元的逻辑状态的虚拟单元布置，其中给定大小的存储单元电容器与每个存储器单元相关联。 在优选实施例中，包括多个虚拟单元，每个虚设单元具有与存储单元电容器大致相同的虚拟电容器。 当要访问存储单元的状态时，其存储单元电容器耦合到位线以改变其上的电压，并且所选择的虚设单元电容器耦合到一对位线，以便实现基本相等的 虚拟电容器和与其耦合的位线之间的电荷。 将存储单元电容器的位线上产生的电压与虚拟电容器的位线之一上的电压进行比较，以确定存取存储单元的逻辑状态。
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公开(公告)号：US4296480A
公开(公告)日：1981-10-20
申请号：US066149
申请日：1979-08-13
IPC分类号： G11C11/406 , H03K21/00 , G11C11/40
CPC分类号： H03K21/00 , G11C11/406
摘要： A refresh counter which uses existing address buffers and is implemented with refresh address storage and decoders. The address buffers act to multiplex the refresh address storage outputs as inverted outputs when properly enabled. When all lower order bits are true at a particular unit of the refresh counter and a transfer clock signal occurs, the outputs of the buffer are transferred to the refresh storage where the buffer multiplexes them when enabled. The clocking scheme is structured to enable only at the end of a refresh cycle. In this manner, the counter is incremented at the end of each refresh cycle.
摘要翻译： 一个使用现有地址缓冲区并用刷新地址存储和解码器实现的刷新计数器。 当正确启用时，地址缓冲区用于将刷新地址存储输出复用为反相输出。 当刷新计数器的特定单元的所有低位都为真时，发生传输时钟信号时，缓冲器的输出将被传送到刷新存储器，当缓冲器使能时，缓冲器的多路复用。 时钟方案的结构只能在刷新周期结束时启用。 以这种方式，计数器在每个刷新周期结束时递增。
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