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公开(公告)号：US07327616B2
公开(公告)日：2008-02-05
申请号：US11235206
申请日：2005-09-27
Applicant: Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
Inventor： Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
IPC: G11C5/14
CPC classification number: G11C16/102
Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.
Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。
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公开(公告)号：US07161850B2
公开(公告)日：2007-01-09
申请号：US11292347
申请日：2005-12-02
Applicant: Hitoshi Shiga , Chih-Hung Wang , Chin Hsi Lin
Inventor： Hitoshi Shiga , Chih-Hung Wang , Chin Hsi Lin
IPC: G11C7/10
CPC classification number: G11C16/344 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C2211/5621
Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。
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公开(公告)号：US07085160B2
公开(公告)日：2006-08-01
申请号：US10958331
申请日：2004-10-06
Applicant: Hitoshi Shiga , Chin Hsi Lin
Inventor： Hitoshi Shiga , Chin Hsi Lin
IPC: G11C16/04
CPC classification number: G11C16/344 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C2211/5621
Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。
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公开(公告)号：US20060083065A1
公开(公告)日：2006-04-20
申请号：US11292347
申请日：2005-12-02
Applicant: Hitoshi Shiga , Chin-Hung Wang , Chin Lin
Inventor： Hitoshi Shiga , Chin-Hung Wang , Chin Lin
IPC: G11C16/04
CPC classification number: G11C16/344 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C2211/5621
Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
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公开(公告)号：US20050276107A1
公开(公告)日：2005-12-15
申请号：US10958331
申请日：2004-10-06
Applicant: Hitoshi Shiga , Chin-Hung Wang , Chin Lin
Inventor： Hitoshi Shiga , Chin-Hung Wang , Chin Lin
CPC classification number: G11C16/344 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C2211/5621
Abstract: A semiconductor memory device includes a memory cell array, data buffer, and column switch. The data buffer senses the potential of a bit line to determine data in a selected memory cell and hold readout data in a read. The data buffer detects both whether the whole data buffer holds “0” data and whether the whole data buffer holds “1” data. The column switch selects part of the data buffer and connects the part to a bus.
Abstract translation: 半导体存储器件包括存储单元阵列，数据缓冲器和列开关。 数据缓冲器检测位线的电位以确定所选择的存储单元中的数据并保持读取中的读出数据。 数据缓冲器检测整个数据缓冲器是否保持“0”数据以及整个数据缓冲器是否保持“1”数据。 列开关选择数据缓冲区的一部分，并将部件连接到总线。
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Patent Agency Ranking
公开(公告)号：US06963501B2
公开(公告)日：2005-11-08
申请号：US10799776
申请日：2004-03-15
Applicant: Hitoshi Shiga
Inventor： Hitoshi Shiga
CPC classification number: G11C16/3454
Abstract: An aspect of the present invention provides a nonvolatile memory that includes a memory cell array including a data storage area to store a data, and a data invert flag storage area to store a data invert flag indicating whether or not the data is inverted. The memory cell array outputs selected data and a data invert flag related to the selected data. A state machine determines whether or not the number of memory cells to which a bias voltage is applied is equal to or greater than a predetermined number when writing data into the memory cell array. The state machine instructs a data controller to transfer inverted data and a data invert flag if it is equal to or greater than the predetermined number.
Abstract translation: 本发明的一个方面提供一种包括存储单元阵列的非易失性存储器，该存储单元阵列包括用于存储数据的数据存储区域和数据反转标志存储区域，以存储指示数据是否反转的数据反转标志。 存储单元阵列输出所选择的数据和与所选数据相关的数据反相标志。 当将数据写入存储单元阵列时，状态机确定施加偏置电压的存储单元的数量是否等于或大于预定数。 如果状态机等于或大于预定数量，则状态机指示数据控制器传送反转数据和数据反转标志。
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47.发明授权公开(公告)号：US06937524B2
公开(公告)日：2005-08-30
申请号：US10461995
申请日：2003-06-11
Applicant: Hitoshi Shiga , Naoya Tokiwa
Inventor： Hitoshi Shiga , Naoya Tokiwa
CPC classification number: G11C16/10 , G11C16/16 , G11C16/3436 , G11C2216/14
Abstract: A non-volatile semiconductor memory device capable of performing page programming at high speeds is provided. This nonvolatile memory device includes a cell array with a matrix of rows and columns of electrically writable and erasable nonvolatile memory cells, and a write control circuit which writes or “programs” one-page data into this cell array at a plurality of addresses within one page. The write control circuit is operable to iteratively perform iteration of a write operation for the plurality of addresses corresponding to one page and iteration of a verify-read operation of the plurality of addresses after writing until verify-read check is passed with respect to every address involved. Regarding an address or addresses with no cells to be written any more, the write control circuit skips the write operation and the after-write verify-read operation.
Abstract translation: 提供能够高速执行页面编程的非易失性半导体存储器件。 这种非易失性存储器件包括具有电可写和可擦除非易失性存储单元的行和列的矩阵的单元阵列，以及一个写入控制电路，其在一个位置内的多个地址中将一页数据写入或“编程”到该单元阵列 页。 写入控制电路可操作以迭代地执行对应于一页的多个地址的写入操作和写入之后多个地址的验证读取操作的迭代，直到相对于每个地址通过验证读取检查 涉及。 关于不再写入单元的地址或地址，写入控制电路跳过写入操作和写入后验证读取操作。
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公开(公告)号：US06928002B2
公开(公告)日：2005-08-09
申请号：US10884739
申请日：2004-07-01
Applicant: Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
Inventor： Hitoshi Shiga , Tokumasa Hara , Tadayuki Taura
CPC classification number: G11C16/107 , G11C16/16 , G11C16/344 , G11C16/3445
Abstract: A non-volatile semiconductor memory device comprises a plurality of blocks each having a plurality of memory cells to be erased at a time and a decoder for selecting the memory cells, each of the blocks having a block decoder for latching a selection signal thereof in pre-programming and for selecting all of the latched blocks by the selection signal at the same time, a sense amplifier, and an address control circuit for controlling a sequence, the sequence including counting addresses of the memory cells in erasing and erasing all of the selected memory cells after pre-programming, all of the blocks having the latched selection signal being controlled to be collectively erased by the address control circuit.
Abstract translation: 一种非易失性半导体存储器件包括多个块，每个块具有一次要擦除的多个存储器单元和用于选择存储器单元的解码器，每个块具有块解码器，用于将其选择信号锁存在预先 编程并用于同时通过选择信号选择所有锁存块，读出放大器和用于控制序列的地址控制电路，该序列包括擦除和擦除所有所选择的所有存储单元的计数地址 预编程后的存储单元，具有锁存选择信号的所有块被控制为由地址控制电路共同擦除。
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49.发明授权Semiconductor integrated circuit device and read start trigger signal generating method therefor 有权半导体集成电路器件及其读取开始触发信号产生方法公开(公告)号：US06903983B2
公开(公告)日：2005-06-07
申请号：US10325753
申请日：2002-12-23
Applicant: Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
Inventor： Tokumasa Hara , Hidetoshi Saito , Hitoshi Shiga , Yasuhiko Honda , Tadayuki Taura , Hideo Kato
CPC classification number: G11C8/18 , G11C16/32 , G11C2216/22
Abstract: A semiconductor integrated circuit device includes a first memory cell array corresponding to bank 0, a second memory cell array corresponding to bank 1, first address transition signal generating circuits which detect transitions of input addresses and generate first address transition signals, a second address transition signal generating circuit which pre-detects an end of automatic execution of bank 0 or bank 1 and generates a second address transition signal, and a read start trigger output circuit. The read start trigger output circuit outputs a read start trigger signal on the basis of the first address transition signals and the second address transition signal.
Abstract translation: 半导体集成电路装置包括对应于存储体0的第一存储单元阵列，对应于存储体1的第二存储单元阵列，检测输入地址的转换并产生第一地址转换信号的第一地址转换信号产生电路，第二地址转换信号 生成电路，其预先检测存储体0或存储体1的自动执行结束并产生第二地址转换信号，以及读取开始触发输出电路。 读取开始触发输出电路基于第一地址转换信号和第二地址转换信号输出读取开始触发信号。
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公开(公告)号：US20050078519A1
公开(公告)日：2005-04-14
申请号：US10799776
申请日：2004-03-15
Applicant: Hitoshi Shiga
Inventor： Hitoshi Shiga
CPC classification number: G11C16/3454
Abstract: An aspect of the present invention provides a nonvolatile memory that includes a memory cell array including a data storage area to store a data, and a data invert flag storage area to store a data invert flag indicating whether or not the data is inverted. The memory cell array outputs selected data and a data invert flag related to the selected data. A state machine determines whether or not the number of memory cells to which a bias voltage is applied is equal to or greater than a predetermined number when writing data into the memory cell array. The state machine instructs a data controller to transfer inverted data and a data invert flag if it is equal to or greater than the predetermined number.
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