公开(公告)号：US20080209110A1

公开(公告)日：2008-08-28

申请号：US12030235

申请日：2008-02-13

Applicant: Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F12/02 ,  G06F12/16

CPC classification number: G06F13/4243 ,  G06F13/4247

Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Abstract translation: 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US20080201548A1

公开(公告)日：2008-08-21

申请号：US12033577

申请日：2008-02-19

Applicant: Steven PRZYBYLSKI ,  Roland SCHUETZ ,  HakJune OH ,  Hong Beom PYEON

Inventor： Steven PRZYBYLSKI ,  Roland SCHUETZ ,  HakJune OH ,  Hong Beom PYEON

IPC: G06F12/00

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

Abstract translation: 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US20080140948A1

公开(公告)日：2008-06-12

申请号：US11624929

申请日：2007-01-19

Applicant: Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

IPC: G06F12/00

CPC classification number: G11C16/20 ,  G11C8/12

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。 每个设备都有其设备类型的设备类型信息。 包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。 在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

公开(公告)号：US20080130386A1

公开(公告)日：2008-06-05

申请号：US11565327

申请日：2006-11-30

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G11C29/40

CPC classification number: G11C29/32 ,  G11C29/003 ,  G11C29/40 ,  G11C2029/0409 ,  G11C2029/2602

Abstract: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.

Abstract translation: 一种用于在多设备系统中对存储器进行高速测试的方法和系统，其中多设备系统的各个设备被布置成串行互连配置。 通过首先将测试模式数据写入多设备系统的每个设备的存储体，然后进行本地测试读取和每个设备中的数据比较来实现高速测试。 每个设备产生表示设备中不存在或存在故障位位置的本地结果数据。 每个设备中的串行测试电路将本地结果数据与来自先前设备的全局结果数据进行比较。 测试电路压缩此比较的结果，并将其作为更新的全局结果数据提供给下一个设备。 因此，更新的全局结果数据将表示所有先前设备的本地结果数据。

公开(公告)号：US06502214B1

公开(公告)日：2002-12-31

申请号：US09386158

申请日：1999-08-31

Applicant: Hong-Beom Pyeon

Inventor： Hong-Beom Pyeon

IPC: G11C2900

CPC classification number: G11C29/26

Abstract: A memory test circuit in a test mode divides a plurality of mats forming a memory and coupled with identical global input/output lines into even and odd-numbered mats and simultaneously activates the even or odd-numbered mats. The memory test circuit sequentially amplifies the activated even or odd-numbered mats, and simultaneously compares the amplified mats in a latch unit, which decreases the memory test time. The memory test circuit can further include a mat controlling unit for dividing a plurality of mats into even and odd-numbered units and simultaneously controlling the even or odd-numbered mats, a mat switch controlling unit for controlling a plurality of mat switches to be sequentially operated, a main amp controlling unit for controlling a plurality of main amps to be sequentially operated, and a latch unit for latching data amplified by the plurality of main amps to be simultaneously outputted.

Abstract translation: 在测试模式中的存储器测试电路将形成存储器并与相同的全局输入/输出线耦合的多个垫分成偶数和奇数编号的垫，同时激活偶数或奇数编号的垫。 存储器测试电路顺序地放大激活的偶数或奇数编号的垫，并同时比较锁存单元中放大的垫，这降低了存储器测试时间。 存储器测试电路还可以包括用于将多个垫分成偶数和奇数单位并同时控制偶数或奇数编号的垫的垫控制单元，用于控制多个垫开关顺序地控制的垫开关控制单元 用于控制要顺序操作的多个主放大器的主放大器控制单元和用于锁存由多个主放大器放大的数据同时输出的锁存单元。

公开(公告)号：US06337816B1

公开(公告)日：2002-01-08

申请号：US09578865

申请日：2000-05-26

Applicant: San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

Inventor： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

IPC: G11C700

CPC classification number: G11C29/846 ,  G11C29/785

Abstract: The present invention relates to a column redundancy circuit for a semiconductor memory whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the normal memory cells and the redundancy data stored in the redundancy memory cells are outputted to a switch unit. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the normal data or redundancy data from the memory array, and outputs it to a main amplifier.

Abstract translation: 本发明涉及一种用于半导体存储器的列冗余电路，其存储器阵列被划分成多个阵列单元，以便以高频适当地工作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在正常存储单元中的正常数据和存储在冗余存储单元中的冗余数据被输出到开关单元。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元从存储器阵列中选择正常数据或冗余数据，并将其输出到主放大器。

公开(公告)号：US5751170A

公开(公告)日：1998-05-12

申请号：US764386

申请日：1996-12-13

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C11/407 ,  G11C7/06 ,  G11C29/04 ,  G11C29/50 ,  G01R19/00

CPC classification number: G11C29/50 ,  G11C29/04 ,  G11C7/06 ,  G11C7/065

Abstract: A circuit for a low voltage sense amplifier obtains a faster test time in designing a circuit because a conventional sense amplifier adopting voltage 3.3V can be applied to a semiconductor memory device requiring a potential of less than 1.0V, and prevents current leakage at a low threshold voltage by providing source voltage to a sense amplifier of a selected memory cell array in an active mode as well as in a standby mode.

Abstract translation: 用于低电压读出放大器的电路在设计电路时获得更快的测试时间，因为采用3.3V电压的传统读出放大器可以应用于需要小于1.0V电位的半导体存储器件，并且可以防止低电流泄漏 通过向处于活动模式以及待机模式的选定存储单元阵列的读出放大器提供源电压来产生阈值电压。

公开(公告)号：US08812768B2

公开(公告)日：2014-08-19

申请号：US12033577

申请日：2008-02-19

Applicant: Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

Inventor： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC: G06F12/00

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

Abstract translation: 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US08526260B2

公开(公告)日：2013-09-03

申请号：US13305064

申请日：2011-11-28

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C7/00

CPC classification number: G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

公开(公告)号：US20130128678A1

公开(公告)日：2013-05-23

申请号：US13425801

申请日：2012-03-21

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G11C7/00

CPC classification number: G11C7/1057 ,  G11C5/04 ,  G11C5/147 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225

Abstract: A semiconductor device comprising (i) internal circuitry for outputting at least one internal clock signal and at least one internal data/control signal for transmission to a next device in a chain of semiconductor devices; (ii) data/control output circuitry for outputting at least one output data/control signal from the at least one internal data/control signal and for releasing the at least one output data/control signal towards the next device via at least one output data/control signal line, the at least one output data/control signal having a first dynamic range; and (iii) clock output circuitry for generating at least one output clock signal from the at least one internal clock signal and for releasing the at least one output clock signal towards the next device via at least one output clock signal line, the at least one output clock signal having a dynamic range different than the first dynamic range.

Abstract translation: 一种半导体器件，包括（i）内部电路，用于输出至少一个内部时钟信号和至少一个内部数据/控制信号，以传输到半导体器件链中的下一个器件; （ii）数据/控制输出电路，用于从至少一个内部数据/控制信号输出至少一个输出数据/控制信号，并用于经由至少一个输出数据向下一个设备释放至少一个输出数据/控制信号 /控制信号线，所述至少一个输出数据/控制信号具有第一动态范围; 以及（iii）时钟输出电路，用于从所述至少一个内部时钟信号产生至少一个输出时钟信号，并且用于经由至少一个输出时钟信号线将所述至少一个输出时钟信号释放到所述下一个器件，所述至少一个 输出时钟信号具有与第一动态范围不同的动态范围。