公开(公告)号：US08731136B2

公开(公告)日：2014-05-20

申请号：US13587287

申请日：2012-08-16

申请人： Hong-Jae Shin ,  Chung-Ah Lee

发明人： Hong-Jae Shin ,  Chung-Ah Lee

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G2310/0286

摘要： Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kth stage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q1, Q2, QB1 and QB2 nodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q1, Q2, QB1 and QB2 nodes.

摘要翻译： 公开了一种门移位寄存器，其可以以减少数量的开关器件执行双向移位操作。 栅极移位寄存器包括多个级以接收多个栅极移位时钟并顺序地输出扫描脉冲。 第k级包括扫描方向控制器，其包括第一和第二正向TFT以及第一和第二反向TFT，以响应于通过第一和第二输入端输入的先前级的进位信号来转换扫描方向，并且传送通过第三和第二输入端输入的下一级的信号， 第四输入端子，包括第一至第十八TFT的节点控制器，用于控制Q1，Q2，QB1和QB2节点的充电和放电操作;以及包括第一和第二上拉TFT的输出单元和第一至第四下拉TFT输出 基于Q1，Q2，QB1和QB2节点的电压电平的两个扫描脉冲。

公开(公告)号：US08624819B2

公开(公告)日：2014-01-07

申请号：US13558025

申请日：2012-07-25

申请人： Jin-Ho Kim ,  Hong-Jae Shin

发明人： Jin-Ho Kim ,  Hong-Jae Shin

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2320/0223

摘要： A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

摘要翻译： 液晶显示器的驱动电路包括：时序控制器，用于输出栅极控制信号和数据控制信号，以控制栅极驱动单元和数据驱动单元的驱动并输出数字视频数据; 一对栅极驱动单元，通过使用至少一个帧作为周期交替地驱动，以响应于栅极控制信号向液晶面板的栅极线提供栅极信号; 以及数据驱动单元，用于响应于数据控制信号将像素信号提供给液晶面板的数据线。 可以防止构成每个栅极驱动器的晶体管的特性的降低。

公开(公告)号：US08384131B2

公开(公告)日：2013-02-26

申请号：US12187271

申请日：2008-08-06

申请人： Kyoung-Woo Lee ,  Andrew Tae Kim ,  Hong-Jae Shin

发明人： Kyoung-Woo Lee ,  Andrew Tae Kim ,  Hong-Jae Shin

IPC分类号： H01L27/10

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

摘要翻译： 半导体器件包括设置在衬底上的熔丝结构。 设置在熔丝结构上的层间电介质。 第一接触插塞，第二接触插塞和第三接触插塞穿透层间电介质，并且其中第一接触插塞，第二接触插塞和第三接触插塞中的每一个连接到熔丝结构。 第一导电图案和第二导电图案设置在层间绝缘体上。 第一导电图案和第二导电图案分别电连接到第一接触插塞和第二接触插塞。

公开(公告)号：US08357576B2

公开(公告)日：2013-01-22

申请号：US13007096

申请日：2011-01-14

申请人： Chong-Kwang Chang ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

发明人： Chong-Kwang Chang ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

公开(公告)号：US20120287112A1

公开(公告)日：2012-11-15

申请号：US13558025

申请日：2012-07-25

申请人： Jin-Ho KIM ,  Hong-Jae Shin

发明人： Jin-Ho KIM ,  Hong-Jae Shin

IPC分类号： G09G3/36 ,  G06F3/038

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2320/0223

摘要： A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

摘要翻译： 液晶显示器的驱动电路包括：时序控制器，用于输出栅极控制信号和数据控制信号，以控制栅极驱动单元和数据驱动单元的驱动并输出数字视频数据; 一对栅极驱动单元，通过使用至少一个帧作为周期交替地驱动，以响应于栅极控制信号向液晶面板的栅极线提供栅极信号; 以及数据驱动单元，用于响应于数据控制信号将像素信号提供给液晶面板的数据线。 可以防止构成每个栅极驱动器的晶体管的特性的降低。

公开(公告)号：US08217393B2

公开(公告)日：2012-07-10

申请号：US12222476

申请日：2008-08-11

申请人： Sun-Jung Lee ,  Hong-Jae Shin

发明人： Sun-Jung Lee ,  Hong-Jae Shin

IPC分类号： H01L23/58 ,  G01R31/26

CPC分类号： G11C29/56 ,  G01R31/2884 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50008 ,  H01L22/34 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed.

摘要翻译： 提供了测试装置，SRAM测试装置，半导体集成电路及其制造方法。 测试装置可以包括在半导体衬底上在一个方向上延伸的第一测试有源区域，除了第一测试有源区域之外的第二测试有源区域，在半导体衬底上沿一个方向延伸，多个测试栅极线穿过测试 活性区域，至少一个测试有源区域和测试栅极线路上的多个测试触点，电连接测试触点的多个导电区域和互连多个测试触点的多个导电布线，其中开放 形成电连接多个测试触点的接触链。

公开(公告)号：US08198702B2

公开(公告)日：2012-06-12

申请号：US13193637

申请日：2011-07-29

申请人： Dong-suk Shin ,  Andrew-Tae Kim ,  Hong-jae Shin

发明人： Dong-suk Shin ,  Andrew-Tae Kim ,  Hong-jae Shin

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

摘要翻译： 本发明一般涉及半导体器件的熔丝器件，更具体地，涉及一种半导体器件的电熔丝器件。 本发明的实施例提供一种能够减少由熔丝链中的不均匀电流密度引起的编程误差的熔丝装置。 在一方面，提供一种电熔丝装置，其包括：阳极; 熔丝链路，其在所述熔丝连接件的第一侧上耦合到所述阳极; 连接到所述熔丝链的第二侧上的所述熔断体的阴极; 耦合到阴极的第一阴极接触; 以及耦合到所述阳极的第一阳极触点，所述第一阴极触点和所述第一阳极触点中的至少一个跨越所述熔断体的虚拟延伸表面设置。

公开(公告)号：US20110195550A1

公开(公告)日：2011-08-11

申请号：US13007096

申请日：2011-01-14

申请人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

发明人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

摘要翻译： 一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

公开(公告)号：US20110074743A1

公开(公告)日：2011-03-31

申请号：US12884771

申请日：2010-09-17

申请人： Mi-Young SON ,  Hong-Jae SHIN

发明人： Mi-Young SON ,  Hong-Jae SHIN

IPC分类号： G09G5/00

CPC分类号： G09G3/20 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/0223

摘要： A gate drive circuit for a display device is disclosed, by which output states of scan pulses are identically maintained in a manner of minimizing load deviation between connecting units. The present disclosure includes at least two clock transmission lines transmitting at least two clock pulses having a phase difference in-between, a shift register outputting scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines, and a plurality of connecting units connecting the clock transmission lines to the shift register, respectively, wherein at least one of the connecting units is zigzagged in part.

摘要翻译： 公开了一种用于显示装置的栅极驱动电路，由此扫描脉冲的输出状态以最小化连接单元之间的负载偏差的方式相同地保持。 本公开内容包括至少两个时钟传输线，其传输在其间具有相位差的至少两个时钟脉冲，移位寄存器基于从时钟传输线传输的时钟脉冲顺序地输出扫描脉冲，以及多个连接单元连接 时钟传输线分别连接到移位寄存器，其中至少一个连接单元部分地是锯齿形的。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。