公开(公告)号：US08381141B2

公开(公告)日：2013-02-19

申请号：US12914212

申请日：2010-10-28

Applicant: Stephen E. Fischer ,  James A. Culp ,  Robert T. Sayah

Inventor： Stephen E. Fischer ,  James A. Culp ,  Robert T. Sayah

IPC: G06F17/50

CPC classification number: G03F7/705

Abstract: A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.

Abstract translation: 在为一组数据准备参数和光刻处理条件生成的模拟光刻图案中识别一组光学规则检查器（ORC）标记。 每个ORC标记识别模拟光刻图案中违反ORC规则的特征。 在每个ORC标记中定义一个中心线，并且在每个中心线周围生成最小尺寸区域，其最小宽度符合ORC的规则。 通过从最小尺寸区域去除与ORC标记重叠的区域，在每个ORC标记周围定义故障区域。 添加所有故障区域的区域以定义模拟光刻图案的特征。 可以通过修改数据准备参数和光刻处理条件的集合来评估多个模拟光刻图案或迭代降低的缺点。

公开(公告)号：US08336008B2

公开(公告)日：2012-12-18

申请号：US12569421

申请日：2009-09-29

Applicant: James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

Inventor： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

Abstract translation: 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US08239790B2

公开(公告)日：2012-08-07

申请号：US13216362

申请日：2011-08-24

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US08141027B2

公开(公告)日：2012-03-20

申请号：US12652409

申请日：2010-01-05

Applicant: James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

Inventor： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

Abstract translation: 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

公开(公告)号：US20120066657A1

公开(公告)日：2012-03-15

申请号：US12880228

申请日：2010-09-13

Applicant: Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

Inventor： Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

Abstract translation: 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

公开(公告)号：US20110098838A1

公开(公告)日：2011-04-28

申请号：US12603679

申请日：2009-10-22

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/10

Abstract: Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

Abstract translation: 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

公开(公告)号：US20110078641A1

公开(公告)日：2011-03-31

申请号：US12569421

申请日：2009-09-29

Applicant: James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

Inventor： James A. Culp ,  Jerry D. Hayes ,  Ying Liu ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Mechanisms are provided for characterizing long range variability in integrated circuit manufacturing. A model derivation component tests one or more density pattern samples, which are a fabricated integrated circuits having predetermined pattern densities and careful placement of current-voltage (I-V) sensors. The model derivation component generates one or more empirical models to establish range of influence of long range variability effects in the density pattern sample. A variability analysis component receives an integrated circuit design and, using the one or more empirical models, analyzes the integrated circuit design to isolate possible long range variability effects in the integrated circuit design.

Abstract translation: 提供了用于表征集成电路制造中的长距离变化的机制。 模型推导部件测试一个或多个密度样本样本，其是具有预定图案密度的制造的集成电路和电流 - 电压（I-V）传感器的仔细放置。 模型推导组件产生一个或多个经验模型，以确定密度模式样本中长距离变异效应的影响范围。 可变性分析组件接收集成电路设计，并且使用一个或多个经验模型分析集成电路设计以隔离集成电路设计中的可能的长距离变化效应。

公开(公告)号：US20100269079A1

公开(公告)日：2010-10-21

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07805693B2

公开(公告)日：2010-09-28

申请号：US12031734

申请日：2008-02-15

Applicant: Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  Anthony D. Polson

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.

Abstract translation: 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。

公开(公告)号：US20090278222A1

公开(公告)日：2009-11-12

申请号：US12117771

申请日：2008-05-09

Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

IPC: H01L27/00 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072

Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

Abstract translation: 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。