公开(公告)号：US20090098697A1

公开(公告)日：2009-04-16

申请号：US12289494

申请日：2008-10-29

Applicant: Sang-min Shin ,  Suk-pil Kim ,  Young-soo Park ,  Jung-hyun Lee ,  June-mo Koo

Inventor： Sang-min Shin ,  Suk-pil Kim ,  Young-soo Park ,  Jung-hyun Lee ,  June-mo Koo

IPC: H01L21/71 ,  H01G9/004

CPC classification number: H01L27/11502 ,  H01L28/55 ,  H01L28/65 ,  Y10T29/417

Abstract: A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer.

Abstract translation: 铁电电容器包括包含Ir和Ru的合金的第一电极，设置在第一电极上的铁电层和设置在铁电层上的第二电极。 铁电存储器包括衬底和布置在衬底上的多个存储单元。 每个存储单元包括包含Ir和Ru的合金的第一电极，设置在第一电极上的铁电层和设置在铁电层上的第二电极。

公开(公告)号：US20080210998A1

公开(公告)日：2008-09-04

申请号：US12068172

申请日：2008-02-04

Applicant: June-mo Koo ,  Bum-seok Seo ,  Young-soo Park ,  Jung-hyun Lee ,  Sang-min Shin ,  Suk-pil Kim

Inventor： June-mo Koo ,  Bum-seok Seo ,  Young-soo Park ,  Jung-hyun Lee ,  Sang-min Shin ,  Suk-pil Kim

IPC: H01L29/92 ,  H01L21/8246

CPC classification number: H01L21/02197 ,  H01L21/0228 ,  H01L21/31691 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

Abstract: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.

Abstract translation: 提供一种能够提高强电介质层上的贵金属层的沉积速度的材料层的制造方法，使用该材料的铁电电容器的制造方法，通过相同的方法制造的铁电电容器以及半导体存储器件 具有铁电电容器及其制造方法。 根据材料层的制造方法，形成铁电体层。 可以将铁电层暴露于种子等离子体，并且可以在暴露于种子等离子体的铁电层的区域上形成包括种子等离子体的源材料的材料层。

公开(公告)号：US20080191264A1

公开(公告)日：2008-08-14

申请号：US12010139

申请日：2008-01-22

Applicant: Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

Inventor： Won-Joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC: H01L29/00 ,  H01L21/3205

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: Non-volatile memory devices highly integrated using an oxide based compound semiconductor and methods of operating and fabricating the same are provided. A non-volatile memory device may include one or more oxide based compound semiconductor layers. A plurality of auxiliary gate electrodes may be arranged to be insulated from the one or more oxide based compound semiconductor layers. A plurality of control gate electrodes may be positioned between adjacent pairs of the plurality of auxiliary gate electrodes at a different level from the plurality of auxiliary gate electrodes. The plurality of control gate electrodes may be insulated from the one or more oxide based compound semiconductor layers. A plurality of charge storing layers may be interposed between the one or more oxide based compound semiconductor layers and the plurality of control gate electrodes.

Abstract translation: 提供了使用基于氧化物的化合物半导体高度集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括一个或多个基于氧化物的化合物半导体层。 多个辅助栅极电极可以布置成与一个或多个氧化物基化合物半导体层绝缘。 多个控制栅电极可以位于与多个辅助栅极电极不同的多个辅助栅电极的相邻对之间。 多个控制栅电极可以与一个或多个氧化物基化合物半导体层绝缘。 可以在一个或多个氧化物基化合物半导体层和多个控制栅电极之间插入多个电荷存储层。

公开(公告)号：US20080025106A1

公开(公告)日：2008-01-31

申请号：US11715404

申请日：2007-03-08

Applicant: Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

Inventor： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined. first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.

Abstract translation: 提供非易失性存储器件的单元电池及其方法。 在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点， 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底。 分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成在第一位线区域和第一存储节点层之间的半导体衬底上的第一遍栅极电极，形成的第二遍栅极电极 在第二位线区域和第二存储节点层之间的半导体衬底上，形成在第一和第二存储节点层之间的半导体衬底上的第三遍栅极电极，形成在半导体衬底的一部分中的第三位线区域 所述第三通道栅极电极和跨越所述第一和第二存储节点层延伸的控制栅极电极。 示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

公开(公告)号：US20080023749A1

公开(公告)日：2008-01-31

申请号：US11724290

申请日：2007-03-15

Applicant: Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

Inventor： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC: H01L29/788 ,  G11C5/14 ,  H01L21/336

CPC classification number: H01L29/42352 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336

Abstract: Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

Abstract translation: 示例性实施例提供了具有增加的集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括多个第一存储节点膜和半导体衬底上的多个第一控制栅电极。 多个第二存储节点膜和多个第二控制栅电极可以凹入到两个相邻的第一控制栅电极之间并且在多个第一控制栅电极的底部之下的半导体衬底中。 多个位线区域可以在半导体衬底上，并且每个可以跨越多个第一控制栅极电极和多个第二控制栅电极延伸。

公开(公告)号：US20070272973A1

公开(公告)日：2007-11-29

申请号：US11709860

申请日：2007-02-23

Applicant: Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

Inventor： Yoon-dong Park ,  June-mo Koo ,  Kyoung-lae Cho

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor memory device includes a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer interposed between a sidewall of the control gate electrode and the semiconductor substrate, a tunneling insulation layer interposed between the storage node layer and the semiconductor substrate, a blocking insulation layer interposed between the storage node layer and the control gate electrode, and first and second channel regions formed around a surface of the semiconductor substrate to at least partially surround the control gate electrode. The semiconductor memory device may include a plurality of control gate electrodes, storage node layers, tunneling insulation layers, blocking insulation layers, and continuous first and second channel regions. A method of fabricating the semiconductor memory device includes etching the semiconductor substrate to form a plurality of holes, forming the tunneling insulation layers, storage node layers, blocking insulation layers, and control gate electrodes.

Abstract translation: 半导体存储器件包括半导体衬底，凹入半导体衬底中的控制栅极电极，插在控制栅电极的侧壁和半导体衬底之间的存储节点层，介于存储节点层和半导体衬底之间的隧道绝缘层 衬底，介于存储节点层和控制栅电极之间的阻挡绝缘层，以及形成在半导体衬底的表面周围以至少部分地围绕控制栅电极的第一和第二沟道区。 半导体存储器件可以包括多个控制栅电极，存储节点层，隧道绝缘层，阻挡绝缘层以及连续的第一和第二沟道区域。 制造半导体存储器件的方法包括蚀刻半导体衬底以形成多个孔，形成隧道绝缘层，存储节点层，阻挡绝缘层和控制栅电极。

公开(公告)号：US20110308455A1

公开(公告)日：2011-12-22

申请号：US13223374

申请日：2011-09-01

Applicant: Hyuk-soon CHOI ,  Hyo-sug LEE ,  June-mo KOO ,  Kwang-hee KIM

Inventor： Hyuk-soon CHOI ,  Hyo-sug LEE ,  June-mo KOO ,  Kwang-hee KIM

IPC: B05C3/10 ,  B05C11/00

CPC classification number: B05D3/0263 ,  B05D1/00 ,  B05D1/185 ,  B05D2401/32 ,  B22F1/0018 ,  B22F1/0062 ,  B22F2998/00 ,  B82Y10/00 ,  B82Y30/00 ,  Y10T428/24355 ,  Y10T428/24372 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/2462 ,  B22F1/0022

Abstract: A method of forming a nano-particle array by convective assembly and a convective assembly apparatus for the same are provided. The method of forming nano-particle array comprises: coating a plurality of nano-particles by forming a coating layer; performing a first convective assembly by moving a first substrate facing, in parallel to and spaced apart from a second substrate at a desired distance such that a colloidal solution including the coated nano-particles is between the first and second substrate; and performing a second convective assembly for evaporating a solvent by locally heating a surface of the colloidal solution drawn when the first substrate is moved in parallel relative to the second substrate. The present invention provides the method of forming the nano-particle array where nano-particles having a particle size from a few to several tens of nanometers are uniformly arrayed on a large area substrate at a low cost, and the convective assembly apparatus for the same.

Abstract translation: 提供了通过对流组装形成纳米颗粒阵列的方法和用于其的对流组装装置。 形成纳米颗粒阵列的方法包括：通过形成涂层来涂覆多个纳米颗粒; 通过将第一衬底移动到与第二衬底平行并间隔开所需距离的方式执行第一对流组件，使得包含涂覆的纳米颗粒的胶体溶液位于第一和第二衬底之间; 以及执行用于蒸发溶剂的第二对流组件，其通过局部加热当所述第一衬底相对于所述第二衬底平行移动时所绘制的所述胶体溶液的表面而蒸发溶剂。 本发明提供了形成纳米粒子阵列的方法，其中纳米粒子具有几个到几十个纳米的粒子以低成本均匀地排列在大面积基底上，而对流装配装置 。

公开(公告)号：US08017991B2

公开(公告)日：2011-09-13

申请号：US11724290

申请日：2007-03-15

Applicant: Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

Inventor： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC: H01L29/788

CPC classification number: H01L29/42352 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336

Abstract: Example embodiments provide a non-volatile memory device with increased integration and methods of operating and fabricating the same. A non-volatile memory device may include a plurality of first storage node films and a plurality of first control gate electrodes on a semiconductor substrate. A plurality of second storage node films and a plurality of second control gate electrodes may be recessed into the semiconductor substrate between two adjacent first control gate electrodes and below the bottom of the plurality of first control gate electrodes. A plurality of bit line regions may be on the semiconductor substrate and each may extend across the plurality of first control gate electrodes and the plurality of second control gate electrodes.

Abstract translation: 示例性实施例提供了具有增加的集成的非易失性存储器件及其操作和制造方法。 非易失性存储器件可以包括多个第一存储节点膜和半导体衬底上的多个第一控制栅电极。 多个第二存储节点膜和多个第二控制栅电极可以凹入到两个相邻的第一控制栅电极之间并且在多个第一控制栅电极的底部之下的半导体衬底中。 多个位线区域可以在半导体衬底上，并且每个可以跨越多个第一控制栅极电极和多个第二控制栅电极延伸。

公开(公告)号：US07986545B2

公开(公告)日：2011-07-26

申请号：US12465125

申请日：2009-05-13

Applicant: Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

Inventor： Tae-eung Yoon ,  Won-joo Kim ,  June-mo Koo ,  Suk-pil Kim ,  Tae-hee Lee

IPC: G11C11/00

CPC classification number: G11C8/14 ,  G11C5/02 ,  G11C5/025

Abstract: A non-volatile memory device having a stack structure, and a method of operating the non-volatile memory device In which the non-volatile memory device includes a plurality of variable resistors arranged in at least one layer. At least one layer selection bit line and a plurality of bit lines coupled to the plurality of the variable resistors are provided. A plurality of selection transistors coupled between the plurality of the bit lines and the plurality of the variable resistors are provided.

Abstract translation: 具有堆叠结构的非易失性存储器件以及操作非易失性存储器件的方法其中非易失性存储器件包括布置在至少一层中的多个可变电阻器。 提供耦合到多个可变电阻器的至少一个层选择位线和多个位线。 耦合在多个位线和多个可变电阻之间的多个选择晶体管被设置。

公开(公告)号：US07947590B2

公开(公告)日：2011-05-24

申请号：US12588064

申请日：2009-10-02

Applicant: Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

Inventor： Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/115 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

Abstract translation: 非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。 桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。 一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。 非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。 至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制 栅电极。