公开(公告)号：US20060109028A1

公开(公告)日：2006-05-25

申请号：US11314236

申请日：2005-12-22

Applicant: Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehia Ismail

Inventor： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehia Ismail

IPC: H03K19/173

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

公开(公告)号：US20060067152A1

公开(公告)日：2006-03-30

申请号：US10954537

申请日：2004-09-29

Applicant: Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

Inventor： Ali Keshavarzi ,  Fabrice Paillet ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De

IPC: G11C17/18 ,  G11C5/06

CPC classification number: G11C17/16

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

公开(公告)号：US20060067133A1

公开(公告)日：2006-03-30

申请号：US10956407

申请日：2004-09-30

Applicant: Yibin Ye ,  Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Gerhard Schrom ,  Vivek De

Inventor： Yibin Ye ,  Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Gerhard Schrom ,  Vivek De

IPC: G11C7/10

CPC classification number: G11C11/404 ,  G11C2211/4016

Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

Abstract translation: 用于单相写入单晶体管存储单元阵列的方法和装置。 在一个实施例中，该方法包括对存储器单元阵列的选定字线的单相写入。 一旦选择了字线，逻辑零值被存储在存储单元阵列的选定字线的至少一个存储单元中。 同时，逻辑0值存储在所选择的存储单元阵列的选定字线的至少一个存储单元中。 描述和要求保护其他实施例。

公开(公告)号：US20060067109A1

公开(公告)日：2006-03-30

申请号：US10956195

申请日：2004-09-30

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen Tang ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  James Tschanz ,  Stephen Tang ,  Vivek De

IPC: G11C5/14 ,  G11C11/00

CPC classification number: G11C11/413

Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.

Abstract translation: 描述了一种方法，其包括至少通过在晶体管处达到运算放大器的反馈回路内的节点上的电压来调制作为其使用的函数的SRAM的功耗。 电压超过另一个电压，运算放大器将驱动节点没有晶体管的帮助。 电压有助于反馈回路在SRAM内的单元上建立一个压降。

公开(公告)号：US20060014331A1

公开(公告)日：2006-01-19

申请号：US10879480

申请日：2004-06-30

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Shih-Lien Lu ,  Brian Doyle ,  Suman Datta ,  Vivek De

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7841

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Abstract translation: 浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。 栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。 栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

公开(公告)号：US06903984B1

公开(公告)日：2005-06-07

申请号：US10748222

申请日：2003-12-31

Applicant: Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

Inventor： Stephen Tang ,  Ali Keshavarzi ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De

IPC: G11C11/404 ,  G11C11/408 ,  H01L27/108 ,  H01L29/78 ,  G11C7/00

CPC classification number: H01L27/108 ,  G11C11/404 ,  G11C11/4085 ,  H01L29/7841

Abstract: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.

Abstract translation: DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。 晶体管具有浮置通道体，其存储对应于两个数字数据值之一的电位。 晶体管还包括连接到第一字线的栅极，连接到第二字线的漏极和连接到位线的源极。 通过将单词和位线设置为特定的电压状态，通道体由于碰撞电离而存储数字一个电位，并且由于体对源结的正向偏置而存储数字零值。

公开(公告)号：US20150279438A1

公开(公告)日：2015-10-01

申请号：US14229767

申请日：2014-03-28

Applicant: Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

Inventor： Jaydeep P. Kulkarni ,  Anupama Thaploo ,  Iqbal Rajwani ,  Kyung-Hoae Koo ,  Eric A. Karl ,  Muhammad Khellah

IPC: G11C7/12 ,  G11C17/16 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

Abstract translation: 实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

公开(公告)号：US08245111B2

公开(公告)日：2012-08-14

申请号：US12331255

申请日：2008-12-09

Applicant: Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

Inventor： Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Chris Wilkerson ,  Wei Wu ,  Dinesh Somasekhar ,  Muhammad Khellah ,  Shih-Lien Lu

IPC: G06F11/00

CPC classification number: H03M13/2921 ,  G06F11/1064 ,  H03M13/1102 ,  H03M13/13 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/2918

Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

Abstract translation: 处理器可以包括高速缓存，其可以在处理器以低功率模式操作时被分成第一和第二部分。 第一部分的高速缓存行可以被分段成段。 第一编码器可以在对数据流的第一部分进行编码的同时产生第一数据位和校验位，并且第二编码器可以分别在编码数据流的第二部分时生成第二数据位和校验位。 第一数据位可以存储在第一部分的第一部分中，并且与第一部分相关联的第二部分的第一部分中的校验位。 第一解码器可以使用存储在第一部分中的校验位来校正第一数据位中的多位位置中的错误，并且第二解码器可以单独地使用第二组校验位对第二数据位进行解码。

公开(公告)号：US20120106285A1

公开(公告)日：2012-05-03

申请号：US13347213

申请日：2012-01-10

Applicant: Vivek De ,  DiaaEldin S. Khalil ,  Muhammad Khellah ,  Moty Mehalel ,  George Shchupak

Inventor： Vivek De ,  DiaaEldin S. Khalil ,  Muhammad Khellah ,  Moty Mehalel ,  George Shchupak

IPC: G11C5/14

CPC classification number: G11C5/142 ,  G11C5/063 ,  G11C11/412 ,  G11C11/413

Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.

Abstract translation: 采用共享供电结构的寄存器文件来提高最小电源电压。

公开(公告)号：US20070058419A1

公开(公告)日：2007-03-15

申请号：US11225912

申请日：2005-09-13

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Nam Kim ,  Yibin Ye ,  Vivek De ,  Kevin Zhang ,  Bo Zheng

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Nam Kim ,  Yibin Ye ,  Vivek De ,  Kevin Zhang ,  Bo Zheng

IPC: G11C11/00

CPC classification number: G11C11/412 ,  Y10S257/903

Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.