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    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby
    7.
    发明授权
    Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby 有权
    通过自对准SI将SIGNA转换过程和结构形成的多晶纳米级晶体管中的单轴应变的方法

    公开(公告)号：US08288233B2

    公开(公告)日：2012-10-16

    申请号：US11864726

    申请日：2007-09-28

    申请人： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    发明人： Been-Yih Jin ,  Brian Doyle ,  Jack Kavalieros ,  Suman Datta

    IPC分类号： H01L21/8244

    CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7848

    摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods may include providing a gate electrode comprising a top surface and first and second laterally opposite sidewalls, wherein a hard mask is disposed on the top surface, a source drain region disposed on opposite sides of the gate electrode, and a spacer disposed on the first and second laterally opposed sidewalls of the gate electrode, forming a silicon germanium layer on exposed portions of the top surface and the first and second laterally opposite sidewalls of the source drain region and then oxidizing a portion of the silicon germanium layer, wherein a germanium portion of the silicon germanium layer is forced down into the source drain region to convert a silicon portion of the source drain region into a silicon germanium portion of the source drain region.

    摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例可以包括提供包括顶表面和第一和第二横向相对的侧壁的栅电极，其中硬掩模设置在顶表面上，源极漏极区域设置在栅电极的相对侧上， 在栅电极的第一和第二横向相对的侧壁上，在源漏区的顶表面和第一和第二横向相对的侧壁的暴露部分上形成硅锗层，然后氧化硅锗层的一部分，其中 硅锗层的锗部分被迫下降到源极漏极区域中，以将源极区域的硅部分转换成源极漏极区域的硅锗部分。

    Methods for uniform doping of non-planar transistor structures
    8.
    发明申请
    Methods for uniform doping of non-planar transistor structures 有权
    均匀掺杂非平面晶体管结构的方法

    公开(公告)号：US20080085580A1

    公开(公告)日：2008-04-10

    申请号：US11529963

    申请日：2006-09-29

    申请人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    发明人： Brian Doyle ,  Robert Chau ,  Suman Datta ,  Jack Kavalieros

    IPC分类号： H01L21/8238 ,  H01L29/94

    CPC分类号： H01L21/823437 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/66803 ,  H01L29/7851

    摘要： Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

    摘要翻译： 用于均匀尖端掺杂非平面晶体管的硅体的方法以及通过这种方法形成的器件和系统。 在一个实施例中，一种方法可以包括在衬底上具有至少三个表面的硅体的垂直尖端离子注入，随后是电介质材料的共形沉积。 可以选择性地蚀刻介电材料以暴露硅体的顶表面，随后选择性地再次氧化顶表面以形成掩模。 可以除去剩余的电介质材料，然后对硅体的至少两个侧壁进行成角度的离子注入。 可以去除掩模，从而产生均匀掺杂的硅体。