公开(公告)号：US09626233B2

公开(公告)日：2017-04-18

申请号：US14260420

申请日：2014-04-24

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： J. Adam Kemp ,  Neil S. Feiereisel ,  Brent C. Schwan

IPC: G06F9/54 ,  G06F13/00 ,  G06F3/00 ,  G06F9/50

CPC classification number: G06F9/544 ,  G06F3/00 ,  G06F9/5022 ,  G06F13/00

Abstract: A graphical program execution environment that facilitates communication between a producer program and a consumer program is disclosed. The producer program may store data in a memory block allocated by the producer program. A graphical program may communicate with the producer program to obtain a reference to the memory block. The graphical program may asynchronously pass the reference to the consumer program, e.g., may pass the reference without blocking or waiting while the consumer program accesses the data in the memory block. After the consumer program is finished accessing the data, the consumer program may asynchronously notify the graphical program execution environment to release the memory block. The graphical program execution environment may then notify the producer program that the block of memory is no longer in use so that the producer program can de-allocate or re-use the memory block.

公开(公告)号：US20170104617A1

公开(公告)日：2017-04-13

申请号：US14879285

申请日：2015-10-09

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Justin R. Magers

IPC: H04L27/20 ,  H04B1/403 ,  H04B1/48 ,  H04L27/227

CPC classification number: H04B1/403 ,  H03C3/40 ,  H03D7/166 ,  H04B1/48 ,  H04L27/206 ,  H04L27/2273 ,  H04L27/364

Abstract: An improved quadrature modulator/demodulator (IQMD) may use two-phase quadrature local oscillator (LO) signal generation for generating 0° and 90° LO signals, and an anti-phase combiner/divider (at 0° and 180°) on the RF (radio frequency) port. The IQMD may include mixers (which may be double-balanced passive mixers) that function as downconverters when a signal is incident at their radio frequency (RF) ports, and function as upconverters when signals are incident on their intermediate frequency (IF) ports. Accordingly, the IQMD may function as an I/Q modulator by connecting digital-to-analog converters (DAC) to the differential I and Q ports, and/or it may also function as an I/Q demodulator by connecting analog-to-digital converters (ADC) to the differential I and Q ports.

公开(公告)号：US09621387B1

公开(公告)日：2017-04-11

申请号：US14879285

申请日：2015-10-09

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Justin R. Magers

IPC: H04B1/38 ,  H04L27/20 ,  H04L27/227 ,  H04B1/403 ,  H04B1/48

CPC classification number: H04B1/403 ,  H03C3/40 ,  H03D7/166 ,  H04B1/48 ,  H04L27/206 ,  H04L27/2273 ,  H04L27/364

Abstract: An improved quadrature modulator/demodulator (IQMD) may use two-phase quadrature local oscillator (LO) signal generation for generating 0° and 90° LO signals, and an anti-phase combiner/divider (at 0° and 180°) on the RF (radio frequency) port. The IQMD may include mixers (which may be double-balanced passive mixers) that function as downconverters when a signal is incident at their radio frequency (RF) ports, and function as upconverters when signals are incident on their intermediate frequency (IF) ports. Accordingly, the IQMD may function as an I/Q modulator by connecting digital-to-analog converters (DAC) to the differential I and Q ports, and/or it may also function as an I/Q demodulator by connecting analog-to-digital converters (ADC) to the differential I and Q ports.

公开(公告)号：US09611797B2

公开(公告)日：2017-04-04

申请号：US13934431

申请日：2013-07-03

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Matthew Viele

IPC: F02D41/20 ,  F02D41/26 ,  F02D41/28

CPC classification number: F02D41/20 ,  F02D41/266 ,  F02D41/28 ,  F02D2041/2006

Abstract: An engine system may include a specified number of injectors and an engine control unit (ECU) having pins to which the injectors may be coupled. The ECU may include a controller implemented in hardware, software, or combination of both, and capable of switching between different multiplexing configurations, where each multiplexing configuration includes a specified number of individual injectors coupled across corresponding pairs of pins. The controller may select one multiplexing configuration from the number of specified multiplexing configurations without requiring any hardware adjustments to be made to the injectors and/or pins. The controller may also operate the individual injectors through the corresponding pairs of pins in an active multiplexing configuration selected by the controller. In at least one multiplexing configuration, the controller may control low-side switches at certain pins of the corresponding pairs of pins, and independent high-side switches at the remaining pins of the corresponding pairs of pins.

公开(公告)号：US20170033915A1

公开(公告)日：2017-02-02

申请号：US14878645

申请日：2015-10-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： James W. McCoy ,  Takao Inoue ,  Jaeweon Kim

IPC: H04L5/14 ,  H04L27/00 ,  H04B1/44 ,  H04L25/08

CPC classification number: H04L5/14 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/294 ,  H03F2200/451 ,  H04B1/0475 ,  H04B1/44 ,  H04B2001/0425 ,  H04L25/08 ,  H04L27/0002 ,  H04L27/368

Abstract: Techniques are disclosed relating to use of digital predistortion in the context of full-duplex radio. In some embodiments, an apparatus includes one or more antennas and is configured to simultaneously transmit and receive wireless signals via at least partially overlapping frequency resources using the one or more antennas. In some embodiments, the apparatus includes receive chain circuitry that is configured to process both wireless signals transmitted by the apparatus via the one or more antennas and over-the-air wireless signals from one or more other computing devices. In some embodiments, the apparatus includes one or more processing elements configured to determine one or more digital predistortion parameters based on the wireless signals transmitted by the apparatus via the one or more antennas and processed by the receive chain circuitry and apply predistortion to transmitted wireless signals based on the one or more digital predistortion parameters.

Abstract translation: 公开了关于在全双工无线电的上下文中使用数字预失真的技术。 在一些实施例中，装置包括一个或多个天线，并且被配置为通过使用一个或多个天线的至少部分重叠的频率资源同时发送和接收无线信号。 在一些实施例中，该设备包括接收链路电路，其被配置为处理由设备经由一个或多个天线发送的无线信号和来自一个或多个其他计算设备的空中无线信号。 在一些实施例中，该装置包括一个或多个处理元件，其被配置为基于由装置经由一个或多个天线发送的并由接收链电路处理的无线信号来确定一个或多个数字预失真参数，并将预失真应用于所发送的无线信号 基于一个或多个数字预失真参数。

公开(公告)号：US09548882B2

公开(公告)日：2017-01-17

申请号：US15072909

申请日：2016-03-17

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Stephen L. Dark ,  Daniel J. Baker ,  Johnathan R. W. Ammerman

IPC: H04L27/38 ,  H04W24/08 ,  H04B17/309 ,  H04B17/21 ,  H04L7/00 ,  H04W56/00 ,  H04W72/04 ,  H04B17/00 ,  H04B1/12

CPC classification number: H04L27/3827 ,  H04B1/12 ,  H04B17/00 ,  H04B17/0085 ,  H04B17/21 ,  H04B17/309 ,  H04L7/0087 ,  H04W24/08 ,  H04W56/003 ,  H04W72/044

Abstract: Various embodiments are described of devices and associated methods for processing a signal using a plurality of vector signal analyzers (VSAs). An input signal may be split and provided to a plurality of VSAs, each of which may process a respective frequency band of the signal, where the respective frequency bands have regions of overlap. Each VSA may adjust the gain and phase of its respective signal such that continuity of phase and magnitude is preserved through the regions of overlap. The correction of gain and phase may be accomplished by a complex multiply with a complex calibration constant. A complex calibration constant may be determined for each VSA by comparing the gain and phase of one or more calibration tones generated with each region of overlap, as measured by each of the VSAs.

Abstract translation: 描述了使用多个向量信号分析器（VSA）处理信号的设备和相关方法的各种实施例。 输入信号可以被分离并提供给多个VSA，每个VSA可以处理信号的相应频带，其中各个频带具有重叠的区域。 每个VSA可以调整其相应信号的增益和相位，使得通过重叠区域保持相位和幅度的连续性。 增益和相位的校正可以通过复数乘以复合校准常数来实现。 可以通过比较由每个VSA测量的每个重叠区域产生的一个或多个校准音调的增益和相位来为每个VSA确定复校正常数。

公开(公告)号：US09477386B2

公开(公告)日：2016-10-25

申请号：US14257944

申请日：2014-04-21

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Yong Rao ,  Ahsan Aziz ,  James W. McCoy

IPC: H03M1/00 ,  G06F3/0484 ,  H03K19/177 ,  H03K19/173 ,  G06F3/0481 ,  H03M1/12

CPC classification number: G06F3/04842 ,  G06F3/04817 ,  H03K19/1733 ,  H03K19/17748 ,  H03M1/1215

Abstract: Various embodiments of methods and associated devices for increasing throughput in a programmable hardware element using interleaved data converters are disclosed. A device comprising a programmable hardware element may be configured to comprise a plurality N of processing portions. The device may receive an input signal, and sample the signal in an interleaved fashion, on a per sample basis, at an effective rate K, to produce N parallel data streams. The N parallel data streams may be processed in parallel by the plurality N of processing portions. Outputs of the plurality N of processing portions may be combined to produce output data. The effective rate K and/or the number N of parallel data streams may be specified by user input. Alternatively, these values may be determined automatically. For example, the effective rate K may be determined automatically based on a bandwidth of the input signal.

Abstract translation: 公开了用于增加使用交错数据转换器的可编程硬件元件中的吞吐量的方法和相关装置的各种实施例。 包括可编程硬件元件的装置可以被配置为包括多个N个处理部分。 设备可以接收输入信号，并且以有效速率K以每个采样的方式以交织的方式对信号进行采样，以产生N个并行数据流。 N个并行数据流可以由多个处理部分并行处理。 可以组合多个N个处理部分的输出以产生输出数据。 并行数据流的有效速率K和/或数量N可以由用户输入来指定。 或者，可以自动确定这些值。 例如，可以基于输入信号的带宽自动确定有效速率K.

公开(公告)号：US20160188518A1

公开(公告)日：2016-06-30

申请号：US15063686

申请日：2016-03-08

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Eric R. Gardiner ,  Jonathan W. Hearn ,  Craig S. Jones ,  Jason D. Tongen

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4045 ,  G06F9/4401 ,  G06F12/0246 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.

Abstract translation: 主机系统可以耦合到PCIe子系统。 在PCIe子系统的设置期间，主机系统中的BIOS可以首先被通知要耦合的设备不是PCIe设备，并且这些设备需要一定量的存储器。 因此，BIOS可能不尝试配置设备，并且可以替代地分配所需的存储器空间。 当操作系统启动时，它可能不会尝试配置设备，加载自定义驱动程序而不是现有的PCI驱动程序来配置总线。 加载后，自定义驱动程序可以配置设备，然后通知操作系统系统中有指定地址的PCIe设备，这可能导致操作系统加载和执行现有的PCIe设备驱动程序来操作/使用设备。 专有驱动程序也可用于处理PCIe驱动程序和操作系统之间的流量。

公开(公告)号：US09361155B2

公开(公告)日：2016-06-07

申请号：US14839439

申请日：2015-08-28

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Sundeep Chandhoke ,  Herbert K. Salmon, IV

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4887 ,  G06F9/4825 ,  G06F2209/486

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract translation: 一种调度时间关键任务的方法和系统。 该系统可以包括处理单元，硬件辅助调度器和耦合到处理单元和硬件辅助调度器两者的存储器。 该方法可以包括接收用于执行时间关键任务的定时信息，时间关键任务通过处理单元的核心上的线程执行程序指令，并且基于接收的定时信息调度时间关键任务。 该方法还可以包括对延迟定时器进行编程，等待唤醒时间来获得和通知处理单元的调度。 此外，该方法可以包括在处理单元的核心上执行根据调度的时间关键任务，监视延迟定时器，以及响应于延迟定时器到期而断言线程执行中断，从而暂停执行 时间关键任务。

公开(公告)号：US09335977B2

公开(公告)日：2016-05-10

申请号：US14050084

申请日：2013-10-09

Applicant: NATIONAL INSTRUMENTS CORPORATION

Inventor： Guoqiang Wang ,  Kaushik Ravindran ,  Rhishikesh Limaye ,  Guang Yang ,  Arkadeb Ghosal ,  Hugo A. Andrade ,  John R. Allen ,  Jacob Kornerup ,  Ian C. Wong ,  Jeffrey N. Correll ,  Michael J. Trimborn

IPC: G06F17/50 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F8/34 ,  G06F9/4494 ,  G06F17/5022 ,  G06F17/505 ,  G06F17/5054

Abstract: System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information.

Abstract translation: 描述了基于访问模式信息优化数据流图的系统和方法。 可以接收数据流程图的访问模式信息。 数据流程图可以包括多个互连的执行者，例如功能块，在视觉上指示数据流图的功能。 访问模式信息可以包括以下中的一个或多个：指定循环的输入模式信息，其中由至少一个参与者消耗令牌，或输出模式信息指定周期中的至少一个角色产生令牌。 可以至少部分地基于访问模式信息来生成实现数据流程图的功能的程序。