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    ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS
    41.
    发明申请
    ADVANCED DETECTION OF MEMORY DEVICE REMOVAL, AND METHODS, DEVICES AND CONNECTORS 有权
    高级检测存储器件移除，以及方法，器件和连接器

    公开(公告)号：US20100312965A1

    公开(公告)日：2010-12-09

    申请号：US12478422

    申请日：2009-06-04

    申请人： James Cooke ,  Peter Feeley ,  Victor Tsai ,  William H. Radke ,  Neal Galbo ,  Chad Cobbley

    发明人： James Cooke ,  Peter Feeley ,  Victor Tsai ,  William H. Radke ,  Neal Galbo ,  Chad Cobbley

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F13/4068

    摘要： Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be specially configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal through which the memory device receives power. Alternatively, the connector may be specially configured to generate a signal that causes a host to terminate programming or erase operations in the memory device prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.

    摘要翻译： 提供了用于终止操作的存储器件，连接器和方法，包括响应于在从诸如插座的连接器移除存储器设备期间接收信号而终止诸如编程或擦除操作之类的内部操作的存储器件。 存储器件可以被特别地配置为产生去除信号，例如通过包括专用的移除终端。 存储卡可以通过在断电之前终止编程或擦除操作来响应信号。 移除终端可以具有不同于存储设备通过其接收电力的功率端子的尺寸的尺寸。 或者，连接器可以被特别地配置成产生一个信号，使得主机在存储卡移除之前终止在存储器设备中的编程或擦除操作，例如通过包括当存储器件移动到预定位置时被致动的开关， 断电位置

    Remapping and compacting in a memory device
    42.
    发明授权
    Remapping and compacting in a memory device 有权
    在存储设备中重映射和压缩

    公开(公告)号：US09146856B2

    公开(公告)日：2015-09-29

    申请号：US13443306

    申请日：2012-04-10

    申请人： Lance Dover ,  Jim Cooke ,  Peter Feeley

    发明人： Lance Dover ,  Jim Cooke ,  Peter Feeley

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F3/065 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/7205 ,  G06F2212/7207

    摘要： Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

    摘要翻译： 公开了用于在存储器件，存储器件和系统中重新映射和/或压缩数据的方法。 一种这样的重新映射和/或压缩数据的方法包括将从主机接收的第一数量的写入操作减少到用于编程的第二数量的写入操作到位于部分页面写入操作的规范内的存储器设备的页面 用于存储设备。 第二数量的写入操作还可以将最初想要编程的数据重新映射到与存储器件的存储器映射相冲突的存储器地址范围。

    Object oriented memory in solid state devices
    43.
    发明授权
    Object oriented memory in solid state devices 有权
    固态设备中面向对象的内存

    公开(公告)号：US08751860B2

    公开(公告)日：2014-06-10

    申请号：US12477349

    申请日：2009-06-03

    申请人： Peter Feeley ,  Neal A. Galbo ,  James Cooke ,  Victor Y. Tsai ,  Robert N. Leibowitz ,  William H. Radke

    发明人： Peter Feeley ,  Neal A. Galbo ,  James Cooke ,  Victor Y. Tsai ,  Robert N. Leibowitz ,  William H. Radke

    IPC分类号： G06F11/08

    CPC分类号： G06F11/1068 ,  G06F11/2064 ,  G06F12/0246 ,  G11C29/52

    摘要： The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

    摘要翻译： 本公开包括固态设备中用于面向对象的存储器的方法，设备和系统。 在固态设备中面向对象存储器的方法的一个实施例包括以原子操作方式访问定义的一组数据作为单个对象，其中访问来自除主机之外的源。 该实施例还包括将定义的一组数据作为单个对象存储在多个固态存储器块中，如由固态存储器块的数量的固态设备的控制部件格式化。

    Memory cell coupling compensation
    44.
    发明授权
    Memory cell coupling compensation 有权
    存储单元耦合补偿

    公开(公告)号：US08681547B2

    公开(公告)日：2014-03-25

    申请号：US13215348

    申请日：2011-08-23

    申请人： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    发明人： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC分类号： G11C16/06

    CPC分类号： G06F11/1068 ,  G06F11/1004 ,  G06F11/1048 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/04 ,  G11C29/52

    摘要： Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

    摘要翻译： 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。

    MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE
    45.
    发明申请
    MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE 有权
    具有三个晶体管存储单元设备的存储器

    公开(公告)号：US20130051142A1

    公开(公告)日：2013-02-28

    申请号：US13217867

    申请日：2011-08-25

    申请人： Koji Sakui ,  Peter Feeley

    发明人： Koji Sakui ,  Peter Feeley

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0408 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

    摘要： Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.

    摘要翻译： 公开了存储器，存储器件以及用于备份序列的方法。 在一个这样的存储器件中，检测电路和页缓冲器耦合在三晶体管存储单元器件和非易失性存储器器件之间。 启用/禁用门使得能够通过三晶体管存储单元设备或非易失性存储器件选择性地访问感测电路和页面缓冲器。

    Methods, devices, and systems for adjusting sensing voltages in devices
    46.
    发明授权
    Methods, devices, and systems for adjusting sensing voltages in devices 有权
    用于调整设备中感应电压的方法，设备和系统

    公开(公告)号：US08358542B2

    公开(公告)日：2013-01-22

    申请号：US13007274

    申请日：2011-01-14

    申请人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    发明人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC分类号： G11C16/06

    CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

    摘要： The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    摘要翻译： 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES
    48.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES 有权
    用于调节设备中感应电压的方法，设备和系统

    公开(公告)号：US20120182810A1

    公开(公告)日：2012-07-19

    申请号：US13007274

    申请日：2011-01-14

    申请人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    发明人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC分类号： G11C16/06

    CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26

    摘要： The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

    摘要翻译： 本公开包括用于调整设备中的感测电压的方法，设备和系统。 一个或多个实施例包括存储器单元和被配置为使用感测电压对存储器单元执行感测操作的控制器，以确定具有大于感测电压的阈值电压（Vt）的存储器单元的数量并且调整感测电压 用于至少部分地基于所确定的存储器单元的数量来确定存储器单元的状态。

    DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS
    49.
    发明申请
    DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 有权
    在存储器件和系统中确定和使用软数据

    公开(公告)号：US20110280084A1

    公开(公告)日：2011-11-17

    申请号：US12778577

    申请日：2010-05-12

    申请人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    发明人： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26 ,  G11C7/14 ,  G11C11/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

    摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

    摘要翻译： 本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。 一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。 控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压： 最少部分地在确定的软数据上。