公开(公告)号：US20250015171A1

公开(公告)日：2025-01-09

申请号：US18895465

申请日：2024-09-25

Applicant: ROHM CO., LTD.

Inventor： Masaki AONO ,  Atsushi NOCHIDA

IPC: H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/861

Abstract: The semiconductor device includes a chip which has a first surface on one side and a second surface on the other side, a plurality of IGBT regions which are provided at an interval in the chip, a boundary region which is provided in a region between the plurality of IGBT regions in the chip, a first conductivity type cathode region which is formed in a surface layer portion of the second surface in the boundary region, and a second conductivity type well region which is formed in a surface layer portion of the first surface in the boundary region.

公开(公告)号：US20250015075A1

公开(公告)日：2025-01-09

申请号：US18896701

申请日：2024-09-25

Applicant: ROHM CO., LTD.

Inventor： Kenichi YOSHIMURA

IPC: H01L27/02

Abstract: A semiconductor device includes: first switching elements arranged in a first direction and each including a first gate wire extending in a second direction; and a back gate guard ring surrounding the first switching elements. The first switching elements are connected to each other in parallel and connected between a first pad and a second pad. The first switching elements include a driver switching element, the driver switching element being at least one first switching element located between two first end switching elements located at opposite ends of the first switching elements in the first direction. The first switching elements excluding the driver switching element include a first protection switching element, the first gate wire of the first protection switching element being connected to the first pad or the second pad.

公开(公告)号：US20250014897A1

公开(公告)日：2025-01-09

申请号：US18758611

申请日：2024-06-28

Applicant: ROHM CO., LTD.

Inventor： Makoto TAKAMURA ,  Takayasu OKA

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/18 ,  H01L21/265 ,  H01L29/16

Abstract: The present disclosure provides a method of manufacturing a semiconductor substrate. The method includes: forming a graphene layer on a silicon plane of a silicon carbide monocrystalline substrate; forming a SiC epitaxial growth layer on the graphene layer; forming a stress layer on the SiC epitaxial growth layer; attaching a temporary substrate onto the stress layer; peeling off the graphene layer from the SiC epitaxial growth layer; forming a SiC polycrystalline growth layer on a carbon plane of the SiC epitaxial growth layer from which the graphene layer has been peeled off; and removing the temporary substrate. At least one of the forming of the graphene layer and the forming of the SiC epitaxial growth layer is under an atmosphere including fluorine.

公开(公告)号：US20250014787A1

公开(公告)日：2025-01-09

申请号：US18896065

申请日：2024-09-25

Applicant: ROHM CO., LTD.

Inventor： Kentaro NAKA

IPC: H01C1/148 ,  H01C7/13 ,  H01C17/245

Abstract: A shunt resistor includes: a resistive element; and a first terminal portion and a second terminal portion. The resistive element has a first end and a second end in a second direction orthogonal to a first direction that is a thickness direction of the resistive element, the second end being an end opposite to the first end, and the resistive element has a third end and a fourth end in a third direction orthogonal to the first direction and the second direction, the fourth end being an end opposite to the third end. The first terminal portion and the second terminal portion are joined to the first end and the second end, respectively.

公开(公告)号：US20250013280A1

公开(公告)日：2025-01-09

申请号：US18897465

申请日：2024-09-26

Applicant: ROHM CO., LTD.

Inventor： Leijie ZHOU ,  Hirofumi INADA

IPC: G06F1/26

Abstract: A PMIC controls multiple power supply circuits. Nonvolatile memory supports repeated writing and has multiple pages. A memory control circuit selects one from among the multiple pages of the nonvolatile memory and writes internal data that indicates an internal state of the power supply management circuit to the write target page. The memory control circuit selects an already-erased page as the write target page and writes the internal data to it, and erases pages other than the write target page.

公开(公告)号：US20250011159A1

公开(公告)日：2025-01-09

申请号：US18898410

申请日：2024-09-26

Applicant: ROHM CO., LTD.

Inventor： Martin Wilfried HELLER ,  Toma FUJITA

IPC: B81B3/00 ,  G01P15/125

Abstract: An acceleration sensor includes a device-side substrate having a first main surface and a second main surface facing the first main surface, a recessed portion recessed from the first main surface toward the second main surface side, a MEMS electrode that is provided in the recessed portion, includes a fixed electrode having a first fixed electrode and a second fixed electrode electrically insulated from the first fixed electrode, and a movable electrode having a first movable electrode and a second movable electrode electrically insulated from the first movable electrode, and constitutes a differential circuit, and an isolation joint that mechanically connects the first movable electrode and the second movable electrode while electrically insulating the first movable electrode and the second movable electrode.

公开(公告)号：US12191275B2

公开(公告)日：2025-01-07

申请号：US18496093

申请日：2023-10-27

Applicant: ROHM CO., LTD.

Inventor： Takukazu Otsuka ,  Seita Iwahashi ,  Maiko Hatano ,  Ryuta Watanabe ,  Katsuhiko Yoshihara

IPC: H01L23/00 ,  H01L23/495

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

公开(公告)号：US20250006580A1

公开(公告)日：2025-01-02

申请号：US18884144

申请日：2024-09-13

Applicant: ROHM CO., LTD.

Inventor： Yuki NAKANO

IPC: H01L23/31 ,  H01L23/29

Abstract: A semiconductor device including a chip having a main surface, a first inorganic film including an insulator and covering the main surface, a second inorganic film including an insulator and covering the first inorganic film, at least one through hole formed in the second inorganic film, and an organic film embedded in the through hole and covering the second inorganic film.

公开(公告)号：US20250006276A1

公开(公告)日：2025-01-02

申请号：US18886194

申请日：2024-09-16

Applicant: ROHM CO., LTD.

Inventor： Seiji TAKENAKA

IPC: G11C16/30

Abstract: A non-volatile memory device includes: a first current mirror having a reference element configured as a memory element for which a program operation can be performed, and a data element configured as the memory element and targeted by the program operation; a reference current generator connected to the data element and configured to generate a reference current; and a storage circuit having the data element and the reference current generator. The storage circuit can read data based on the magnitude relationship between the current flowing through the data element and the reference current.

公开(公告)号：US12183663B2

公开(公告)日：2024-12-31

申请号：US18510204

申请日：2023-11-15

Applicant: ROHM CO., LTD.

Inventor： Kazuki Okuyama ,  Shuntaro Takahashi ,  Motoharu Haga ,  Shingo Yoshida ,  Kazuhisa Kumagai ,  Hajime Okuda

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.