公开(公告)号：US12021516B2

公开(公告)日：2024-06-25

申请号：US17245635

申请日：2021-04-30

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Yoshinori Fukuda

IPC: H03K17/687 ,  H01L29/06 ,  H01L29/78

CPC classification number: H03K17/6871 ,  H01L29/0696 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.

公开(公告)号：US09570603B2

公开(公告)日：2017-02-14

申请号：US14936666

申请日：2015-11-09

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Yasushi Hamazawa

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/7813 ,  H01L21/76895 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/535 ,  H01L23/544 ,  H01L24/06 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66734 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.

Abstract translation: 本发明的半导体器件包括其中形成栅极沟槽的半导体层，沿着栅极沟槽的内表面形成的栅极绝缘膜，通过栅极绝缘膜掩埋在栅极沟槽中的栅电极，并且 具有在下电极和上电极之间的中间绝缘膜彼此上下分离的下电极和上电极，以及形成在栅极沟槽中以穿过上电极的栅极接触 并且通过中间绝缘膜并且到达下电极并且将下电极和上电极电连接在一起。

公开(公告)号：US11450752B2

公开(公告)日：2022-09-20

申请号：US16831791

申请日：2020-03-26

Applicant: ROHM CO., LTD.

Inventor： Yoshinori Fukuda ,  Hajime Okuda ,  Yuji Osumi

IPC: H01L29/41 ,  H01L29/49 ,  G05F1/46 ,  H01L29/861

Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.

公开(公告)号：US10707155B2

公开(公告)日：2020-07-07

申请号：US16156845

申请日：2018-10-10

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Yoshinori Fukuda

IPC: H01L23/495 ,  H01L21/762 ,  H01L21/76 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.

公开(公告)号：US10177134B2

公开(公告)日：2019-01-08

申请号：US15906313

申请日：2018-02-27

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Motoharu Haga ,  Kenji Fujii

IPC: H01L27/02 ,  H01L29/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/373

Abstract: A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed.

公开(公告)号：US12183663B2

公开(公告)日：2024-12-31

申请号：US18510204

申请日：2023-11-15

Applicant: ROHM CO., LTD.

Inventor： Kazuki Okuyama ,  Shuntaro Takahashi ,  Motoharu Haga ,  Shingo Yoshida ,  Kazuhisa Kumagai ,  Hajime Okuda

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

公开(公告)号：US12021012B2

公开(公告)日：2024-06-25

申请号：US17044658

申请日：2019-04-11

Applicant: ROHM CO., LTD.

Inventor： Kazuki Okuyama ,  Shuntaro Takahashi ,  Motoharu Haga ,  Shingo Yoshida ,  Kazuhisa Kumagai ,  Hajime Okuda

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/765 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/48 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2924/13091

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

公开(公告)号：US10374047B2

公开(公告)日：2019-08-06

申请号：US15889507

申请日：2018-02-06

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Adrian Joita

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739 ,  H01L27/092 ,  H01L21/265 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.

公开(公告)号：US09941266B2

公开(公告)日：2018-04-10

申请号：US15379615

申请日：2016-12-15

Applicant: ROHM CO., LTD.

Inventor： Hajime Okuda ,  Motoharu Haga ,  Kenji Fujii

IPC: H01L27/02 ,  H01L29/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/373

CPC classification number: H01L27/0255 ,  H01L23/3171 ,  H01L23/3736 ,  H01L23/49811 ,  H01L23/49838 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed.