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111 条记录 (耗时 0.024 秒)

    Memory devices using tri-state buffers to discharge data lines, and methods of operating same
    41.
    发明授权
    Memory devices using tri-state buffers to discharge data lines, and methods of operating same 失效
    使用三态缓冲器来释放数据线的存储器件，以及操作方法

    公开(公告)号：US07254061B2

    公开(公告)日：2007-08-07

    申请号：US11153508

    申请日：2005-06-15

    申请人： Sang-Wan Nam ,  Seung-Keun Lee

    发明人： Sang-Wan Nam ,  Seung-Keun Lee

    IPC分类号： G11C16/00

    CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106

    摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

    摘要翻译： 存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。 感测放大器电路感测并放大存储器单元的电流。 三态缓冲器接收读出放大器电路的输出。 数据锁存电路锁存三态缓冲器的输出。 数据线连接三态缓冲器和数据锁存电路。 存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。

    NOR flash memory and related read method
    42.
    发明申请
    NOR flash memory and related read method 有权
    NOR闪存及相关读取方式

    公开(公告)号：US20070171723A1

    公开(公告)日：2007-07-26

    申请号：US11606029

    申请日：2006-11-30

    申请人： Sang-wan Nam ,  Dae-han Kim

    发明人： Sang-wan Nam ,  Dae-han Kim

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26

    摘要： A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

    摘要翻译： 公开了一种NOR闪存，其包括存储单元，读出放大器输出驱动器和控制电路。 由读出放大器执行的感测操作的感测周期与时钟信号同步，以避免由输出驱动器的操作产生的电源或接地信号噪声。

    Nonvolatile memory device and method of operating the same
    46.
    发明授权
    Nonvolatile memory device and method of operating the same 有权

    公开(公告)号：US09620232B2

    公开(公告)日：2017-04-11

    申请号：US15130237

    申请日：2016-04-15

    申请人： Sang-Wan Nam

    发明人： Sang-Wan Nam

    IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/11582

    CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  H01L27/11582

    摘要： According to example embodiments, an operation method of a nonvolatile memory device includes determining a location of a selected word line among word lines connected to the nonvolatile memory device, selecting one of a plurality of different read disturbance reducing modes according to the location of the selected word line, and performing a read or verification operation according to the selected read disturbance reducing modes. The nonvolatile memory device includes cell strings. Each one of the cell strings includes memory cells stacked on top of each other in a direction perpendicular to the substrate and between a ground select transistor and a string select transistor. The ground select transistor is between the substrate and the number of the memory cells. The string select transistor is connected to a bit line and is between the bit line and the number of the memory cells.

    NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF
    48.
    发明申请
    NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF 审中-公开
    非易失性存储器件及其驱动方法

    公开(公告)号：US20160365149A1

    公开(公告)日：2016-12-15

    申请号：US15172929

    申请日：2016-06-03

    申请人： SANG-WAN NAM ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

    发明人： SANG-WAN NAM ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

    IPC分类号： G11C16/08 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

    摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

    摘要翻译： 根据发明构思的示例实施例，非易失性存储器件包括存储单元阵列，地址解码器，输入/输出电路，电压产生电路和控制逻辑。 存储单元阵列包括在衬底上的多个存储块。 每个存储块包括连接在位线和公共源极线之间的多个串。 地址解码器被配置为测量所选择的存储器块的字线的阻抗信息。 电压产生电路被配置为产生要施加到字线的字线电压，并且字线电压中的至少一个包括偏移电压和目标电压。 控制逻辑被配置为根据测得的字线的阻抗信息来调整偏移电压和偏移时间的电平。

    Nonvolatile memory device
    50.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US09391088B2

    公开(公告)日：2016-07-12

    申请号：US14674188

    申请日：2015-03-31

    申请人： Sang-Wan Nam

    发明人： Sang-Wan Nam

    IPC分类号： H01L27/115 ,  H01L29/82 ,  G11C16/04 ,  G11C11/34

    CPC分类号： H01L27/1157 ,  G11C16/14 ,  G11C16/3427 ,  H01L27/11575 ,  H01L27/11582

    摘要： The nonvolatile memory device includes a plurality of memory cells being stacked in a direction perpendicular to a substrate. A string select transistor is connected between the memory cells and a bit line. A string select line is connected to the string select transistor. A one directional device is connected between the substrate and the string select line and configured to transmit a bias voltage from the substrate toward the string select line in an erase operation.

    摘要翻译： 非易失性存储器件包括沿垂直于衬底的方向堆叠的多个存储器单元。 一个串选择晶体管被连接在存储单元和位线之间。 串选择线连接到串选择晶体管。 单向器件连接在衬底和串选择线之间，并被配置为在擦除操作中从衬底向串选择线发送偏置电压。