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    Method of reducing standby current during power down mode
    41.
    发明授权
    Method of reducing standby current during power down mode 失效

    公开(公告)号：US06665219B2

    公开(公告)日：2003-12-16

    申请号：US10199130

    申请日：2002-07-22

    Applicant: Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    Inventor： Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    IPC: G11C700

    CPC classification number: G11C5/14

    Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

    Method of reducing standby current during power down mode
    42.
    发明授权
    Method of reducing standby current during power down mode 有权
    降低待机电流的方法

    公开(公告)号：US06438060B1

    公开(公告)日：2002-08-20

    申请号：US09780606

    申请日：2001-02-12

    Applicant: Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    Inventor： Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    IPC: G11C700

    CPC classification number: G11C5/14

    Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

    Abstract translation: 一种用于在断电模式操作期间通过中断延迟线的时钟转换来降低存储器集成电路的功耗的装置和方法。 存储器集成电路可以包括延迟锁定环，其包括串联连接并且适于延迟自由运行时钟的信号的传播的多个延迟元件。 当不需要延迟信号时，如在断电模式操作期间，防止自由运行的时钟信号到达延迟锁定环路。 因此，延迟元件不切换，并且节省与延迟元件切换相关联的功率。

    Memory device having circuitry for initializing and reprogramming a control operation feature
    43.
    发明授权
    Memory device having circuitry for initializing and reprogramming a control operation feature 失效
    具有用于初始化和重新编程控制操作特征的电路的存储器件

    公开(公告)号：US5905909A

    公开(公告)日：1999-05-18

    申请号：US783379

    申请日：1997-01-13

    Applicant: Brett Williams ,  Scott Schaefer

    Inventor： Brett Williams ,  Scott Schaefer

    IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4072 ,  G11C11/4096 ,  G06F13/00

    CPC classification number: G11C5/066 ,  G11C11/4072 ,  G11C11/4096 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1072

    Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.

    Abstract translation: 一种具有用于接收第一命令和第二命令并具有初始化和重新编程电路的主控制电路的同步动态随机存取存储器（SDRAM）装置。 主控制电路响应于第一命令产生和初始化信号，并且响应于第二命令产生重编程信号。 初始化和重编程电路响应于初始化信号以控制控制操作特征的初始编程，并响应重编程信号以控制控制操作特征的重新编程。

    Synchronous DRAM memory with asynchronous column decode
    45.
    发明授权
    Synchronous DRAM memory with asynchronous column decode 失效

    公开(公告)号：US5751656A

    公开(公告)日：1998-05-12

    申请号：US772974

    申请日：1996-12-23

    Applicant: Scott Schaefer

    Inventor： Scott Schaefer

    IPC: G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/408

    CPC classification number: G11C7/22 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18

    Abstract: Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.

    Memory array using selective device activation
    46.
    发明授权
    Memory array using selective device activation 失效
    使用选择性设备激活的内存阵列

    公开(公告)号：US5566122A

    公开(公告)日：1996-10-15

    申请号：US407721

    申请日：1995-03-20

    Applicant: Scott Schaefer

    Inventor： Scott Schaefer

    IPC: G11C7/22 ,  G11C8/12 ,  G11C7/00

    CPC classification number: G11C7/22 ,  G11C8/12

    Abstract: A memory array for an electronic device comprises a design which requires fewer memory devices to be activated to access a plurality of data bits, thereby reducing the amount of power required to access the data bits. The design comprises the use of a plurality of memory devices, each of which has a plurality of arrays and data out lines.

    Abstract translation: 用于电子设备的存储器阵列包括需要更少的存储器件被激活以访问多个数据位的设计，从而减少访问数据位所需的功率量。 该设计包括使用多个存储器件，每个存储器件具有多个阵列和数据输出线。

    Memory devices having programmable elements with accurate operating parameters stored thereon
    49.
    发明授权
    Memory devices having programmable elements with accurate operating parameters stored thereon 失效
    存储器件具有存储在其上的精确操作参数的可编程元件

    公开(公告)号：US08339888B2

    公开(公告)日：2012-12-25

    申请号：US13276592

    申请日：2011-10-19

    Applicant: Jeffrey W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

    Inventor： Jeffrey W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

    IPC: G11C17/18

    CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

    Abstract: A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system.

    Abstract translation: 具有存储器件的系统具有用于配置存储器系统的可编程元件。 更具体地，位于存储器件上的诸如反熔丝的可编程元件在制造期间被编程，其中测量的操作参数对应于存储器件。 操作参数可以包括例如工作电流值，工作电压或时序参数。 存储器件被并入到系统中。 一旦存储器件被并入到系统中，可编程元件可以由处理器访问，使得存储器系统可以被配置为根据对系统中的存储器件测量的操作参数进行最佳操作。

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