Abstract:
A power amplifier (PA) envelope power supply and a process to select a converter operating mode of the PA envelope power supply are disclosed. The PA envelope power supply operates in one of a first converter operating mode and a second converter operating mode. The process for selecting the converter operating mode is based on a selected communications mode of a radio frequency (RF) communications system, a target output power from RF PA circuitry of the RF communications system, and a direct current (DC) power supply voltage.
Abstract:
A power amplifier (PA) envelope power supply, radio frequency (RF) PA circuitry, and a process to select a converter operating mode of the PA envelope power supply based on linearity requirements of the RF PA circuitry is disclosed. The PA envelope power supply operates in one of a first converter operating mode and a second converter operating mode. The process for selecting the converter operating mode is based on a required degree of linearity of the RF PA circuitry. The PA envelope power supply provides an envelope power supply signal to the RF PA circuitry. Selection of the converter operating mode may provide efficient operation of the PA envelope power supply and the envelope power supply signal needed for proper operation of the RF PA circuitry.
Abstract:
A radio frequency (RF) power amplifier (PA) amplifying transistor of an RF PA stage and an RF PA temperature compensating bias transistor of the RF PA stage are disclosed. The RF PA amplifying transistor includes a first array of amplifying transistor elements and a second array of amplifying transistor elements. The RF PA temperature compensating bias transistor provides temperature compensation of bias of the RF PA amplifying transistor. Further, the RF PA temperature compensating bias transistor is located between the first array and the second array. As such, the RF PA temperature compensating bias transistor is thermally coupled to the first array and the second array. The RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor.
Abstract:
Circuitry, which includes multi-mode multi-band radio frequency (RF) power amplification circuitry, power amplifier (PA) control circuitry, and a PA-digital communications interface (DCI) is disclosed according to one embodiment of the circuitry. The PA control circuitry is coupled between the amplification circuitry and the PA-DCI, which is coupled to a digital communications bus, and configures the amplification circuitry. The amplification circuitry includes at least a first RF input and multiple RF outputs, such that at least some of the RF outputs are associated with multiple communications modes and at least some of the RF outputs are associated with multiple frequency bands. Configuration of the amplification circuitry associates one RF input with one RF output, and is correlated with configuration information defined by at least a first defined parameter set. The PA control circuitry stores at least a first look-up table (LUT), which provides the configuration information.
Abstract:
A power amplifier (PA) controller semiconductor die and a first radio frequency (RF) PA semiconductor die are disclosed. The PA controller semiconductor die includes a first electro-static discharge (ESD) protection circuit, which ESD protects and provides a first ESD protected signal. The RF PA semiconductor die receives the first ESD protected signal. In one embodiment of the PA controller semiconductor die, the first ESD protected signal is an envelope power supply signal. The PA controller semiconductor die may be a Silicon complementary metal-oxide-semiconductor (CMOS) semiconductor die and the RF PA semiconductor die may be a Gallium Arsenide semiconductor die.
Abstract:
An in-phase radio frequency (RF) power amplifier (PA) stage and a quadrature-phase RF PA stage are disclosed. The in-phase RF PA stage includes a first group of arrays of amplifying transistor elements and the quadrature-phase RF PA stage includes a second group of arrays of amplifying transistor elements. A group of array bias signals is based on a selected one of a group of DDS operating modes. Each of the group of array bias signals is a current signal. The in-phase RF PA stage biases at least one of the first group of arrays of amplifying transistor elements based on the group of array bias signals. Similarly, the quadrature-phase RF PA stage biases at least one of the second group of arrays of amplifying transistor elements based on the group of array bias signals.
Abstract:
A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.
Abstract:
A battery powered radio device includes a transmitter, a control circuit, and a lockout circuit. The transmitter transmits radio communications and the transmitter includes a power amplifier which generates an amplified radiofrequency output signal. More particularly, the power amplifier uses both a positive supply voltage and a negative bias voltage for operation wherein the negative bias voltage is less than a supply ground voltage. The control circuit enables the power amplifier during transmission, and the control circuit includes a switch coupled in series between a positive supply voltage and the power amplifier. The switch is activated in response to a transmit activation signal when the negative bias voltage is coupled to the power amplifier. The lockout circuit prevents activation of the switch in response to the transmit activation signal when the negative bias voltage is not coupled to the power amplifier. In addition, the switch can be activated in response to a transmit activation signal by applying the negative bias voltage to the switch control gate and deactivated in the absence of the transmit activation signal by applying the positive supply voltage to the switch control gate.
Abstract:
Circuitry, which includes multi-mode multi-band radio frequency (RF) power amplification circuitry, power amplifier (PA) control circuitry, and a PA-digital communications interface (DCI) is disclosed according to one embodiment of the circuitry. The PA control circuitry is coupled between the amplification circuitry and the PA-DCI, which is coupled to a digital communications bus, and configures the amplification circuitry. The amplification circuitry includes at least a first RF input and multiple RF outputs, such that at least some of the RF outputs are associated with multiple communications modes and at least some of the RF outputs are associated with multiple frequency bands. Configuration of the amplification circuitry associates one RF input with one RF output, and is correlated with configuration information defined by at least a first defined parameter set. The PA control circuitry stores at least a first look-up table (LUT), which provides the configuration information.
Abstract:
A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.