公开(公告)号：US07298659B1

公开(公告)日：2007-11-20

申请号：US11147791

申请日：2005-06-07

Applicant: Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Sanjiv Kainth

Inventor： Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Sanjiv Kainth

IPC: G11C29/00

CPC classification number: G11C29/06 ,  G11C11/41 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401 ,  G11C2029/1202

Abstract: A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Abstract translation: 描述用于测试用于数据保持故障的易失性存储单元阵列（例如，SRAM）的各个存储单元的方法和系统。 在本发明的一个实施例中，通过一对公共位线连接的相邻存储器单元被写入相对或互补的数据，例如逻辑“0”和逻辑“1”。 接下来，通过对连接两个相邻的存储单元的公共位线进行预充电然后同时断言每个存储单元的字线，对两个存储单元进行应力条件。 最后，读取每个单元格中的数据并将其与在产生应力条件之前写入单元格的数据进行比较。

公开(公告)号：US06452834B1

公开(公告)日：2002-09-17

申请号：US09782490

申请日：2001-02-13

Applicant: Subramani Kengeri

Inventor： Subramani Kengeri

IPC: G11C700

CPC classification number: G11C11/405

Abstract: A 2T dual-port dynamic random access memory (DRAM) that can be fabricated using a pure logic process. Write/Refresh port is independent for any DRAM cell of the DRAM. Sense amplifier is built into each DRAM cell.

Abstract translation: 可以使用纯逻辑过程制造的2T双端口动态随机存取存储器（DRAM）。 写入/刷新端口对于DRAM的任何DRAM单元是独立的。 每个DRAM单元内置有感应放大器。

公开(公告)号：US06442098B1

公开(公告)日：2002-08-27

申请号：US09778382

申请日：2001-02-06

Applicant: Subramani Kengeri

Inventor： Subramani Kengeri

IPC: G11C800

CPC classification number: G11C7/1072 ,  G11C8/12

Abstract: Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the virtual memory banks has coupled to it an associated segmented sense amp which responds to an appropriate bank select signal by sensing data stored in a selected memory bank segment. The segmented sense amp uses a segmented bit line to reduce bit sense latency without decreasing bit density or increasing chip size.

Abstract translation: 公开了用于提供诸如SDRAM的存储器件，其具有逻辑耦合以形成虚拟存储体的分布式存储体区段的装置，方法和系统。 每个虚拟存储体已经耦合到其相关联的分段感测放大器，其通过感测存储在选择的存储体段中的数据来响应适当的存储体选择信号。 分段感测放大器使用分段位线来减少位感测等待时间，而不会降低位密度或增加芯片大小。

公开(公告)号：US06411538B1

公开(公告)日：2002-06-25

申请号：US09727527

申请日：2000-11-28

Applicant: Subramani Kengeri

Inventor： Subramani Kengeri

IPC: G11C1500

CPC classification number: G11C15/04

Abstract: A load-less 12-T TCAM wherein a TCAM cell uses two 1-bit 4-T SRAM storage cells that are scalable with technology. The TCAM has a TCAM cell that comprises two 1-bit 4-T SRAM data storage cells and a comparator. Within the TCAM cell, each of the two 1-bit 4-T SRAM storage cells is coupled to a BL by a pass-gate PMOS transistor that has a NP drain diode section. This NP drain diode section has a reverse-biased leakage current that is adapted to keep a dynamic node of the SRAM storage cell high without relying on any resistive-load element. The comparator is coupled to these two 1-bit 4-T SRAM storage cells. The comparator is adapted for matching a reference data with data communicated to the comparator from the two SRAM storage cells. The comparator is a 4-T comparator coupled to these two 4-T SRAM storage cells, thereby making the TCAM a 12-T load-less static TCAM.

Abstract translation: 一种无负载的12-T TCAM，其中TCAM单元使用两种可通过技术进行扩展的1位4-T SRAM存储单元。 TCAM具有包括两个1位4-T SRAM数据存储单元和比较器的TCAM单元。 在TCAM单元中，两个1位4-T SRAM存储单元中的每一个通过具有NP漏极二极管部分的通过栅极PMOS晶体管耦合到BL。 该NP漏极二极管部分具有反向偏置的漏电流，其适于使SRAM存储单元的动态节点保持高电平，而不依赖于任何电阻负载元件。 比较器耦合到这两个1位4-T SRAM存储单元。 比较器适于将参考数据与从两个SRAM存储单元传送到比较器的数据进行匹配。 比较器是一个4-T比较器，耦合到这两个4-T SRAM存储单元，从而使TCAM成为12-T无负载的静态TCAM。

公开(公告)号：US06288922B1

公开(公告)日：2001-09-11

申请号：US09637124

申请日：2000-08-11

Applicant: Hing Wong ,  Subramani Kengeri

Inventor： Hing Wong ,  Subramani Kengeri

IPC: G11C1500

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: The invention discloses a low-power ternary CAM by utilizing four encoded comparand datalines, C0, C1, C2, and C3 in a twin ternary cell. The twin ternary cell is a composite of two ternary CAM bits. The two binary CAM bits are coded so that only one of four comparand datalines is toggled during a compare operation. The encoded data is stored and used for comparison. In one embodiment, the four possible states for the 2 bit comparands are coded as 0001, 0010, 0100, and 1000.

Abstract translation: 本发明公开了一种低功率三元CAM，通过在双三进制单元中利用四个编码的比较数据，C0，C1，C2和C3。 双胞胎单元是两个三进制CAM位的组合。 两个二进制CAM位被编码，使得在比较操作期间只切换四个比较数据的一个。 编码数据被存储并用于比较。 在一个实施例中，用于2比较比较的四种可能状态被编码为0001，0010，0100和1000。

公开(公告)号：US6108250A

公开(公告)日：2000-08-22

申请号：US293494

申请日：1999-04-15

Applicant: Subramani Kengeri

Inventor： Subramani Kengeri

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/789 ,  G11C29/84

Abstract: A high speed process for determining whether an externally applied address points to a memory cell or a redundant memory cell in a memory is disclosed. Identification information associated with redundant memory rows and columns is stored and compared with decoded information based upon a decoded externally applied address. This comparison determines if a memory cell of a redundant memory cell is addressed.

Abstract translation: 公开了用于确定外部施加的地址是指向存储器中的存储器单元还是冗余存储器单元的高速处理。 与冗余存储器行和列相关联的识别信息基于解码的外部应用地址被存储并与解码信息进行比较。 该比较确定冗余存储器单元的存储单元是否被寻址。

公开(公告)号：US20190326219A1

公开(公告)日：2019-10-24

申请号：US16502521

申请日：2019-07-03

Applicant: Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285 ,  H01L27/02 ,  H01L21/768

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US20140183638A1

公开(公告)日：2014-07-03

申请号：US13729843

申请日：2012-12-28

Applicant: Mahbub RASHED ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub RASHED ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211

Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

Abstract translation: 公开了使用分段沟槽自对准硅层选择性地连接翅片结构的方法，以及所得到的装置。 实施例包括：在衬底上提供至少一个栅极结构; 在与所述至少一个栅极结构相交的垂直方向上提供第一和第二鳍结构; 以及提供自对准层的第一段，所述第一段沿着水平方向形成并且与所述第二鳍结构连接并与所述第一鳍结构分离。

公开(公告)号：US08689154B2

公开(公告)日：2014-04-01

申请号：US13446418

申请日：2012-04-13

Applicant: Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

Inventor： Mahbub Rashed ,  David Doman ,  Dinesh Somasekhar ,  Yan Wang ,  Yunfei Deng ,  Navneet Jain ,  Jongwook Kye ,  Ali Keshavarzi ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.

Abstract translation: 公开了一种从平面设计提供定时关闭的FinFET设计的方法。 实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。 其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

公开(公告)号：US08631365B2

公开(公告)日：2014-01-14

申请号：US13461571

申请日：2012-05-01

Applicant: Subramani Kengeri ,  Chung-Cheng Chou ,  Bharath Upputuri ,  Hank Cheng ,  Ming-Zhang Kuo ,  Pey-Huey Chen

Inventor： Subramani Kengeri ,  Chung-Cheng Chou ,  Bharath Upputuri ,  Hank Cheng ,  Ming-Zhang Kuo ,  Pey-Huey Chen

IPC: G06F9/45

CPC classification number: G06F17/5045

Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract translation: 存储器构建块可以与ASIC自动设计工具结合使用，以使用已知ASIC设计流程来生成存储器宏（例如，存储器阵列），其包括例如寄存器传输级（RTL），合成，自动位置和路由 （APR）和时序分析。