公开(公告)号：US20100161058A1

公开(公告)日：2010-06-24

申请号：US12344212

申请日：2008-12-24

申请人： Mahmoud F. Abdelgany ,  Aaron D. Markworth ,  Young Hoon Oh

发明人： Mahmoud F. Abdelgany ,  Aaron D. Markworth ,  Young Hoon Oh

IPC分类号： A61F2/44

CPC分类号： A61F2/442 ,  A61F2002/30471 ,  A61F2002/30563 ,  A61F2002/30565 ,  A61F2002/30581 ,  A61F2002/30841 ,  A61F2220/0091 ,  A61F2310/00011 ,  A61F2310/00023

摘要： A multiple-state geometry artificial disc assembly attached to vertebrae includes a compliant load bearing spacer element having an upper curved portion and a lower curved portion, a first plate coupled on the upper curved portion of the compliant load bearing spacer element and a second plate coupled on the lower curved portion of the compliant load bearing spacer element. The first plate and the second plate preferably are of a flexible material. The first plate and the second plate transitions from a convex configuration to a concave configuration in-situ in a vertebral disc space. The upper curved portion and the lower curved portion of the compliant load bearing spacer element may include a plurality of openings. The compliant load bearing spacer element may further include a middle cylindrical portion dimensioned and configured to match a gap between the first plate and the second plate.

摘要翻译： 附接到椎骨的多状态几何人造椎盘组件包括具有上弯曲部分和下弯曲部分的顺从承载间隔元件，联接在柔性承载间隔元件的上弯曲部分上的第一板和耦合 在柔性负载隔离元件的下弯曲部分上。 第一板和第二板优选为柔性材料。 第一板和第二板在椎间盘空间中原位从凸形状转变为凹形构型。 柔性负载隔离元件的上弯曲部分和下弯曲部分可以包括多个开口。 柔性承载间隔元件还可以包括尺寸和构造成匹配第一板和第二板之间的间隙的中间圆柱形部分。

公开(公告)号：US20090115475A1

公开(公告)日：2009-05-07

申请号：US12217002

申请日：2008-06-30

申请人： Young-Hoon Oh

发明人： Young-Hoon Oh

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0812 ,  H03L7/093

摘要： A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

摘要翻译： 半导体器件的延迟锁定环（DLL）具有相对小的面积和低的电流消耗，同时具有校正占空比的功能。 所述半导体器件包括分配单元，其被配置为接收和分离参考时钟以输出对应于所述参考时钟的第一边缘的第一时钟和对应于第二边缘的第二时钟;电压生成单元，被配置为生成对应于 对应于第一时钟的占空比和对应于第二时钟的占空比的第二电压，电压比较单元，被配置为将第一和第二电压的电平彼此进行比较;以及时钟延迟单元，被配置为接收 用于响应于电压比较单元的输出信号来确定延迟量的接收时钟的第一和第二时钟。

公开(公告)号：US07492645B2

公开(公告)日：2009-02-17

申请号：US11527440

申请日：2006-09-27

申请人： Khil-Ohk Kang ,  Young-Hoon Oh

发明人： Khil-Ohk Kang ,  Young-Hoon Oh

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/147

摘要： An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.

摘要翻译： 提供了一种用于半导体存储器件的内部电压发生器。 内部电压发生器包括用于产生第一参考电压的第一参考电压发生器，用于产生第二参考电压的第二参考电压发生器，用于基于第一参考电压提高核心电压的核心电压发生器，以及核心电压放电器 用于根据第二参考电压放电核心电压。

公开(公告)号：US06436960B1

公开(公告)日：2002-08-20

申请号：US09601426

申请日：2000-08-01

申请人： You Seung Shin ,  Jong Sung Koh ,  Hyun Il Lee ,  Jin Ho Lee ,  Jong Hyun Kim ,  Hyun Ho Chung ,  Kwi Hwa Kim ,  Tae Hwan Kwak ,  Seong Gu Ro ,  In Ae Ahn ,  Tae Saeng Choi ,  Young Hoon Oh ,  Chung Mi Kim ,  Sun Hwa Lee ,  Hyun Sung Kim

发明人： You Seung Shin ,  Jong Sung Koh ,  Hyun Il Lee ,  Jin Ho Lee ,  Jong Hyun Kim ,  Hyun Ho Chung ,  Kwi Hwa Kim ,  Tae Hwan Kwak ,  Seong Gu Ro ,  In Ae Ahn ,  Tae Saeng Choi ,  Young Hoon Oh ,  Chung Mi Kim ,  Sun Hwa Lee ,  Hyun Sung Kim

IPC分类号： A61K31454

CPC分类号： C07D401/14 ,  C07D417/14

摘要： The present invention relates to a novel piperidine derivative represented by formula (1) which shows an inhibitory activity against farnesyl transferase or pharmaceutically acceptable salts thereof, in which A, E and G are defined in the specification; to a process for preparation of the compound of formula (1); to an intermediate which is used in the preparation of the compound of formula (1); and to a pharmaceutical composition comprising the compound of formula (1) as an active ingredient.

摘要翻译： 本发明涉及式（1）所示的新型哌啶衍生物，其表现出对法呢基转移酶的抑制活性或其药学上可接受的盐，其中A，E和G在本说明书中定义; 涉及制备式（1）化合物的方法; 涉及用于制备式（1）化合物的中间体; 以及包含式（1）化合物作为活性成分的药物组合物。

公开(公告)号：USRE44632E1

公开(公告)日：2013-12-10

申请号：US13538130

申请日：2012-06-29

申请人： Young-Hoon Oh ,  Kwang-Myoung Rho

发明人： Young-Hoon Oh ,  Kwang-Myoung Rho

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

公开(公告)号：US07868675B2

公开(公告)日：2011-01-11

申请号：US12761739

申请日：2010-04-16

申请人： Young-Hoon Oh

发明人： Young-Hoon Oh

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0812 ,  H03L7/093

摘要： A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

公开(公告)号：US07791392B2

公开(公告)日：2010-09-07

申请号：US11646343

申请日：2006-12-28

申请人： Young-Hoon Oh

发明人： Young-Hoon Oh

IPC分类号： H03K3/00

CPC分类号： H03K5/135 ,  H03K5/19

摘要： An apparatus for generating a pulse which generates an internal signal. The apparatus includes a latch circuit latching an input signal to output a first signal. A clock period detector detects a period of an external clock signal to output a period detecting signal and a delay controller adjusts a delay time of the first signal to output a second signal in response to the period detecting signal. A signal generator receives the first signal and the second signal to output a pulse signal.

摘要翻译： 一种用于产生产生内部信号的脉冲的装置。 该装置包括锁存输入信号以输出第一信号的锁存电路。 时钟周期检测器检测外部时钟信号的周期以输出周期检测信号，并且延迟控制器响应于周期检测信号调整第一信号的延迟时间以输出第二信号。 信号发生器接收第一信号和第二信号以输出脉冲信号。

公开(公告)号：US20100174322A1

公开(公告)日：2010-07-08

申请号：US12348283

申请日：2009-01-03

申请人： Mahmoud F. Abdelgany ,  Young Hoon Oh

发明人： Mahmoud F. Abdelgany ,  Young Hoon Oh

IPC分类号： A61B17/04

CPC分类号： A61B17/7037

摘要： A dynamic screw assembly includes a screw head having a pair of diametrically opposed arms, a slot between the arms, an inwardly curved bottom portion, an outwardly protruding and expandable bulbous end extending from the inwardly curved bottom portion and an opening positioned through the bulbous end, a bumper mechanism adjacent to the screw head that adjusts an angle of the screw head to a desired location in the dynamic screw assembly, a fixation component coupled to the bumper mechanism, a saddle connection positioned in the opening and engaging the screw head and the fixation component, a longitudinal member positioned in the slot and a blocker coupled to the screw head and the longitudinal member.

摘要翻译： 动态螺钉组件包括具有一对直径相对的臂的螺钉头，臂之间的狭槽，向内弯曲的底部部分，从向内弯曲的底部部分延伸的向外突出和可扩展的球形端部以及穿过球形端部的开口 与所述螺钉头相邻的保险杠机构，其将所述螺钉头的角度调整到所述动态螺钉组件中的期望位置，联接到所述保险杠机构的固定部件，位于所述开口中并与所述螺钉头接合的马鞍连接件 固定部件，定位在所述槽中的纵向构件和联接到所述螺钉头部和所述纵向构件的阻挡件。

公开(公告)号：US07746723B2

公开(公告)日：2010-06-29

申请号：US12354158

申请日：2009-01-15

申请人： Young-Hoon Oh ,  Kwang-Myoung Rho

发明人： Young-Hoon Oh ,  Kwang-Myoung Rho

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

摘要翻译： 半导体存储器件包括：用于将延迟锁定环（DLL）时钟延迟预定延迟时间的可变延迟，以输出延迟的DLL时钟; 输出驱动器，用于响应于延迟的DLL时钟输出数据和数据选通信号; 以及校准控制器，用于响应于输出AC参数来控制可变延迟的预定延迟时间。

公开(公告)号：US07688123B2

公开(公告)日：2010-03-30

申请号：US11826648

申请日：2007-07-17

申请人： Young-Hoon Oh

发明人： Young-Hoon Oh

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03H11/265 ,  H03L7/0805 ,  H03L7/095

摘要： A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be varied, which are set according to initial state setting signals, and increases or decreases the set delay amounts according to a phase detecting signal after the initial operation, a phase comparator that compares a phase of any one of the plurality of clocks and a phase of any one of the plurality of clocks delayed by the register controlled delay part and outputs the phase detecting signal, and an initial state setting unit that generates the initial state setting signals.

摘要翻译： 提供延迟装置和延迟锁定环电路以及使用其的半导体存储装置。 延迟锁定环电路包括寄存器控制延迟部分，其延迟初始操作期间输入的多个时钟，根据初始状态设置信号设定的要改变的初始延迟量之间的延迟量，并且增加或减少设置延迟 根据初始操作之后的相位检测信号的量;相位比较器，其比较多个时钟中的任一个的相位和由寄存器控制延迟部分延迟的多个时钟中的任一个的相位，并输出相位检测 信号，以及初始状态设定单元，其生成初始状态设定信号。