公开(公告)号：US10191852B2

公开(公告)日：2019-01-29

申请号：US15273432

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/00 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

公开(公告)号：US10085214B2

公开(公告)日：2018-09-25

申请号：US15008229

申请日：2016-01-27

Applicant: APPLE INC.

Inventor： Richard M. Solotke ,  Saurabh Garg ,  Haining Zhang

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/166

Abstract: Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive “wake” requests from the peripheral processor.

公开(公告)号：US10078361B2

公开(公告)日：2018-09-18

申请号：US14879024

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F8/00 ,  G06F1/32 ,  G06F13/42 ,  G06F9/4401 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20170249163A1

公开(公告)日：2017-08-31

申请号：US15273398

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F13/42 ,  G06F1/24 ,  G06F9/445

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20170249098A1

公开(公告)日：2017-08-31

申请号：US15273432

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F1/24 ,  G06F3/0626 ,  G06F3/0637 ,  G06F3/0665 ,  G06F3/0683 ,  G06F8/63 ,  G06F12/1441 ,  G06F13/4282 ,  G06F2212/1008 ,  G06F2212/1052 ,  G06F2212/1056 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

公开(公告)号：US09693238B2

公开(公告)日：2017-06-27

申请号：US14257915

申请日：2014-04-21

Applicant: Apple Inc.

Inventor： Ming Hu ,  Haining Zhang ,  Christian W. Mucke

IPC: H04W24/02 ,  H04B1/04 ,  H04B1/18

CPC classification number: H04W24/02 ,  H04B1/0458 ,  H04B1/18

Abstract: Apparatus and methods for the design and dynamic tuning of antenna circuitry for use across multiple radio frequency bands in wireless communication devices is disclosed herein. An antenna apparatus includes antenna tuning control, antenna tuning circuitry, and a set of one or more physical antennas. The antenna tuning controller includes a combination of baseband and front-end hardware and software. The antenna circuitry collectively includes antenna tuning circuitry and the set of one or more physical antennas. Based on a set of radio frequency bands and on communication channel conditions, the antenna tuning controller determines an optimal antenna tuning configuration and provides appropriate parameters to the antenna tuning circuitry. The antenna apparatus configures and optimizes the tuning of the antenna circuitry for a future time period, which can be a next time slot. The antenna tuning controller utilizes a cost/gain function to calculate the optimal antenna tuning configuration.

公开(公告)号：US20160103743A1

公开(公告)日：2016-04-14

申请号：US14879030

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US20150305035A1

公开(公告)日：2015-10-22

申请号：US14257915

申请日：2014-04-21

Applicant: APPLE INC.

Inventor： Ming Hu ,  Haining Zhang ,  Christian W. Mucke

IPC: H04W72/04 ,  H04W24/02

CPC classification number: H04W24/02 ,  H04B1/0458 ,  H04B1/18

Abstract: Apparatus and methods for the design and dynamic tuning of antenna circuitry for use across multiple radio frequency bands in wireless communication devices is disclosed herein. An antenna apparatus includes antenna tuning control, antenna tuning circuitry, and a set of one or more physical antennas. The antenna tuning controller includes a combination of baseband and front-end hardware and software. The antenna circuitry collectively includes antenna tuning circuitry and the set of one or more physical antennas. Based on a set of radio frequency bands and on communication channel conditions, the antenna tuning controller determines an optimal antenna tuning configuration and provides appropriate parameters to the antenna tuning circuitry. The antenna apparatus configures and optimizes the tuning of the antenna circuitry for a future time period, which can be a next time slot. The antenna tuning controller utilizes a cost/gain function to calculate the optimal antenna tuning configuration.

Abstract translation: 本文公开了用于在无线通信设备中的多个无线电频带上使用的天线电路的设计和动态调谐的装置和方法。 天线装置包括天线调谐控制，天线调谐电路和一组一个或多个物理天线。 天线调谐控制器包括基带和前端硬件和软件的组合。 天线电路集体地包括天线调谐电路和一组一个或多个物理天线。 基于一组无线电频带和通信信道条件，天线调谐控制器确定最佳天线调谐配置并且向天线调谐电路提供适当的参数。 天线装置配置和优化天线电路在未来时间段内的调谐，后续时间可能是下一个时隙。 天线调谐控制器利用成本/增益功能来计算最佳天线调谐配置。