公开(公告)号：US12007895B2

公开(公告)日：2024-06-11

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11868258B2

公开(公告)日：2024-01-09

申请号：US18160575

申请日：2023-01-27

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US20230083397A1

公开(公告)日：2023-03-16

申请号：US18058105

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US20230063676A1

公开(公告)日：2023-03-02

申请号：US17657524

申请日：2022-03-31

Applicant: Apple Inc.

Inventor： Sagi Lahav ,  Lital Levy - Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

IPC: G06F9/46 ,  G06F9/32 ,  G06F9/50 ,  G06F9/30

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.

公开(公告)号：US20230058989A1

公开(公告)日：2023-02-23

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasan Rangan Sridharan

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/128

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US11544193B2

公开(公告)日：2023-01-03

申请号：US17315725

申请日：2021-05-10

Applicant: Apple Inc.

Inventor： James Vash ,  Gaurav Garg ,  Brian P. Lilly ,  Ramesh B. Gunna ,  Steven R. Hutsell ,  Lital Levy-Rubin ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar

IPC: G06F12/0815 ,  G06F12/0831

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

公开(公告)号：US20220318136A1

公开(公告)日：2022-10-06

申请号：US17648071

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy - Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/06 ,  G06F12/0891 ,  G06F12/0831 ,  G06F13/16 ,  G06F9/46

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

公开(公告)号：US11138111B2

公开(公告)日：2021-10-05

申请号：US16129527

申请日：2018-09-12

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Srinivasa Rangan Sridharan ,  Harshavardhan Kaushikkar ,  Sridhar Kotha ,  Brian P. Lilly

IPC: G06F12/0815 ,  G06F12/0884 ,  G06F12/0855

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

公开(公告)号：US10795818B1

公开(公告)日：2020-10-06

申请号：US16418811

申请日：2019-05-21

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Per H. Hammarlund ,  Brian P. Lilly ,  Michael Bekerman ,  James Vash ,  Manu Gulati ,  Benjamin K. Dodge

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0817

Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

公开(公告)号：US10678691B2

公开(公告)日：2020-06-09

申请号：US16124713

申请日：2018-09-07

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang

IPC: G06F12/0855

Abstract: Systems, apparatuses, and methods for implementing coherence flows for dual-processing coherence and memory cache pipelines are disclosed. A dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. When a transaction is issued to the dual-processing pipeline, the coherence processing pipeline performs a duplicate tag lookup in parallel with the memory cache processing pipeline performing a memory cache tag lookup for the transaction. If the duplicate tag lookup is a hit, then the coherence processing pipeline locks the matching entry, the memory cache processing pipeline discards the original transaction, and a copyback request is sent to a coherent agent identified by the matching entry. When the copyback response is received by a communication fabric, the copyback response is issued to the memory cache processing pipeline. When the copyback response passes the global ordering point, the coherence processing pipeline clears the lock on the matching entry.